hi,
is this error log means a crash ?
*[ERROR]*:...
# openlaneb
Burak Aykenar
07/18/2022, 2:13 PMhi,
is this error log means a crash ?
[ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: kill signal
[ERROR]: Flow failed.
this is the repo:
https://github.com/mbaykenar/first_asic
i have difficulties in global routing phase, i tried different config options, absolute or relative FP_SIZING, different FP_CORE_UTIL and PL_TARGET_DENSITY values. I always got congestion error. Then i added
set ::env(GLB_RT_ALLOW_CONGESTION) 1
but this time again in global routing i got errors that i have written above
any suggestion is appreciated:
config.tcl parameters:
set ::env(DESIGN_IS_CORE) 0
set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_NET) "pulpino_top_wrapper.clk"
set ::env(CLOCK_PERIOD) "200"
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 40
set ::env(PL_RESIZER_MAX_CAP_MARGIN) 40
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) 40
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2500 2500"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(SYNTH_STRATEGY) "AREA 1"
set ::env(PL_BASIC_PLACEMENT) 0
set ::env(PL_TARGET_DENSITY) 0.3
set ::env(FP_CORE_UTIL) {30}
set ::env(PL_MACRO_CHANNEL) {30 30}
set ::env(PL_MACRO_HALO) {10 10}
set ::env(CELL_PAD) {2}
set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {60}
set ::env(ROUTING_CORES) {6}
set ::env(GLB_RT_OVERFLOW_ITERS) {100}
set ::env(GLB_RT_ALLOW_CONGESTION) 1
macro.cfg:
pulpino_top.core_region_i.data_mem.open_ram_2k 1000 300 N
pulpino_top.core_region_i.instr_mem.sp_ram_wrap_i.open_ram_2k 1000 1500 N
m
Mitch Bailey
07/18/2022, 2:29 PMHi @Burak Aykenar, in the past
child killedDIE_AREAv
Vijayan Krishnan
07/19/2022, 5:49 AM@Burak Aykenar Increase the swap space and run the flow again. https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1650317104192279?thread_ts=1650215768.620859&cid=C016H8WJMBR check the link the swap space increase doc.
Vijayan Krishnan
07/19/2022, 6:01 AM@Burak Aykenar Few more question.
1. Are you going to harden or its a final wrapper design?
b
Burak Aykenar
07/19/2022, 6:36 AMhimm, i have problems on understanding what is hardening and what is final wrapper. i think it is the final wrapper, the top module is "pulpino_top_wrapper" and it is the counterpart of "user_project_wrapper" file.
i mean the ports are:
Burak Aykenar
07/19/2022, 6:36 AMmodule pulpino_top_wrapper
(
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// IRQ
output [2:0] irq
);
Burak Aykenar
07/19/2022, 6:36 AMfrom hardening i understand that the design will be hardened as gds and will be used as a macro ?
v
Vijayan Krishnan
07/19/2022, 6:43 AMOk. Then update following settings
Vijayan Krishnan
07/19/2022, 6:45 AMset ::env(DESIGN_IS_CORE) 1
set ::env(DIE_AREA) "0 0 2700 3200"
Vijayan Krishnan
07/19/2022, 6:47 AMfollow this guide lines for wrapper: https://github.com/efabless/caravel_user_project/tree/main/openlane/user_project_wrapper/fixed_dont_change
Vijayan Krishnan
07/19/2022, 6:52 AMfrom hardening i understand that the design will be hardened as gds and will be used as a macroVijayan Krishnan
07/19/2022, 7:01 AMhttps://github.com/efabless/caravel_user_project/blob/main/openlane/user_project_wrapper/config.tcl update this file based on your input. So it can use full die size given by caravel.
b
Burak Aykenar
07/19/2022, 7:06 AMthanks a lot. but i am a bit confused, i assume that first i will harden my design with (DESIGN_IS_CORE) 1 and DIE_AREA 2700 x 3200, then i will update upw/config.tcl with my gds, lef and verilog netlist files ?
v
Vijayan Krishnan
07/19/2022, 7:10 AMFor hardening
(DESIGN_IS_CORE) 0RT_MAX_LAYER met4b
Burak Aykenar
07/19/2022, 2:22 PMwell this time i am getting "Detailed placement failed on: ANTENNA*" errors. it is difficult and time consuming to change config parameters and wait for the results while praying there will be no error
maybe the problem is the design is over 100K cell without 2 2K SRAM macros. is it a good idea to first harden smaller sub-modules and then go to flow ?
v
Vijayan Krishnan
07/20/2022, 6:45 AMyes you can do it. But make sure of using right layers for routing. During hardening you're allowed to use till
met4👍 1
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