Hello a) I'm still a bit confused by the sky130_stdcells. It seems that there are latches and flipflops, but if I go to their spice netlist the lenghts are around l=150000u, is this to compate for the "Scale is set to 1e-06 "? so that is it still minimal size ? or is this ridigulous big for a reason I don't get yet? b) I want to use a standart cell for my SAR logic, but they seems to exisit out of around 30 transisotrs ( the dfbnn_1,) which is quite a lot I thought? ( my reference is that I moddeled them to be 8 minimal invertors). Does it make sense to take these standart cells for this aplication, or is it better to make them myself? I want to generate a clock frequency of 600 Mhz with them while keeping power as low as possible. Falls this in the medium or high speed category, or will the low power already suffice? c) I don't get the dfbnn_1 to work properly. I thought it was a DFF with active low set and reset and which reacts on the negatieve clock edges. But it doesn't works like that. The outputs are not even complementary and don't behave as a FF at all. what did I do or interpreted wrong? in attachement, the schematic , waveform and spice netlist have a nice day.

Multiple questions here, so I will try to tackle and answer them in turn. (a) Yes, there is a

.option scale=1e-6

buried in the SPICE models which means that all of the values for W and L are given in units of microns (the weird use of "u" in magic's output as in "l=150000u" is a quirk of the way magic formats its output, but it is correct. Magic was not written with the expectation that someone would put a scale option in the middle of the model files. . . (b) Most standard cell flops will buffer the set/reset/clock inputs twice so as to ensure accurate timing of the complementary signals. This adds a lot of extra transistors to the cell but ensures the reliability of the flop. But the cells are known good in real silicon, so redesigning cells yourself will add unnecessary risk. So I would recommend using the existing standard cells unless you have an overriding good reason to squeeze every last square micron out of your design. 600MHz is pretty aggressive for 130nm but it's all hand designed and your logic chains are short, it may be possible. I do not have a recommendation for which standard cell family to use, but my suspicion is that you will need to use the high speed library.

Thank you very much! That explains all!

@Faedra Webers standard cells in xschem have no explicit power pins, however they have attributes so you can hook up these to any power nets you need. There are attributes for VCC/VSS supplies as well as body (well) connections. You can change attributes to :

name=x29 VGND=VGND VNB=VGND VPB=VPWR VPWR=VPWR prefix=sky130_fd_sc_hd__

so you need to provide only 2 power supplies in your schematic, either by placing

vsource.sym

components or writing the following 2 lines in your simulator commands/testbench:

VVPWR VPWR 0 1.8

VVGND VGND 0 0