I am working on fully characterizing the power PMO...
# analog-design
w
I am working on fully characterizing the power PMOS and NMOS that were taped out as part of my buck converter. In particular I am interested in the beta of the parasitic PNP transistor and the reverse recovery characteristics of the well diodes. My initial measurements show beta << 1 and the reverse recovery charge is negligible. Somewhat dubious of the reverse recovery charge measurement, not sure if I need to slew the diode faster with higher current. Does anyone know ballpark figures for what I should expect? Neither of these are modeled in the PDK at all.