Hi, Anyone know how can I run an analysis post layout?, I ran LVS and I have the netlist of xschem and .spice of magic, but when I add .spice of magic with .include / that doesn't work

What is the error?

@Juan Andres: You will need to have pins (ports) marked on the layout, and you will need to declare the port index of each one (using the

port make

and

port index

commands) so that the order of ports matches between the schematic and the layout. Otherwise, you will get a random order of pins that works for LVS (because all pins have the correct names in both netlists) but not for simulation (because the port order is different when the cell is instantiated). The other way to do it is just to check what the port order is in the layout netlist and rearrange the ports in the simulation testbench to match it.

You could make a wrapper circuit so you don't have to worry about the pin order. xschem netlist.

.subckt top A B C D E F
...
.ends

extracted netlist

.subckt top B C A F D E
...
.ends

test bench spice

Xtop_wrapper A B C D E F top_wrapper

* .include xschem/top.spice
.include extracted/top.spice

.subckt top_wrapper A B C D E F
* xschem simulation
*Xtop A B C D E F top
* extracted simulation
Xtop B C A F D E top
.ends