Hi @Tim Edwards / @Stefan Schippers, got a query regarding transients on chip startup. How do we ensure a particular value at an analog circuit node while the chip starts up ? Basically , we dont want any stray voltages to disturb our nodes (lets say any terminal of reram) , so grounding the voltage at design , then changing as per configuration. is there any specialized circuit for that OR it has to be controlled through POR ? Thanks

Generally, you'll want a power-on-reset circuit to make sure that the power supply is up and stable before you enable any analog functions. Of course, the power-on-reset is an analog function itself. It really depends on how sensitive the analog circuit is to power supply changes. The ESD circuitry will prevent analog circuits from encountering anything truly destructive. it's mostly about circuits with potential metastable states like (poorly designed) bandgaps from powering up into an incorrect state.

@Ryan R some systems have a reset pin and require power up with reset pin asserted. After power is stable reset is released. For systems with no reset pin a POR circuit as explained by @Tim Edwards is used.

@Tim Edwards, so even before power-on , is there any way to ground the nodes ? (or doesnt make sense to do it - since there will not be any stray voltages since there is no power supply to the core ?? )

@Ryan R once you have a signal that is logic high during power on (when VCC is ramping up) and goes down when VCC is sufficiently high you just can use a NMOS pull down on nodes you want to keep grounded (see right part of picture). Picture below shows also a possible on-chip Power On Reset generation, that guarantees a correct POR signal for any type of VCC ramp up slope (and locks out the circuit when VCC goes again below a certain threshold). Some implementations avoid the use of a big resistor and rely on a capacitor only, to avoid static consumption (usually in the range of 500nA). However zero consumption POR circuits can fail in some weird power-up sequences and do not perform lockout when VCC drops below the minimum threshold.

Thanks @Stefan Schippers , seems the caravel example has a POR which uses the POR of top caravel. // Power-on-reset signal. The reset pad generates the sense-inverted // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are // derived. wire porb_h; wire porb_l; wire por_l; // Power-on-reset circuit simple_por por ( `ifdef USE_POWER_PINS .vdd3v3(vddio_core), .vdd1v8(vccd_core), .vss3v3(vssio_core), .vss1v8(vssd_core), `endif .porb_h(porb_h), .porb_l(porb_l), .por_l(por_l) ); Does this mean caravel's signals porb_h, porb_l are not power on reset signals . and we need to generate POR from them ?

@Ryan R for the caravel POR implementation i leave comments to people who know how it is done :-)

Hi @Tim Edwards , in user_analog_project_wrapper i dont see any POR signal coming from core side (because the power supplies to the risc core and other components are different ? ) . hence ideally we need to build our own correct , if we are using vdda1/vdda2 etc. Is this understanding correct

You can use the management SoC to read the "powergood" signals on the user project supplies, and implement some behavior resulting in a power-on-reset signal that you would apply through the logic analyzer interface. That's the use case I've had in mind for applying a reset to the user project.

@Tim Edwards , are there any detailed waveforms for power-up of the full caravel ?

Not in analog. The GPIO cells are massively complicated and full analog simulation is practically impossible at the top level. We have simulated some of the power cells but that doesn't really capture the full power-up behavior.