Hi everyone! Could people provide feedback on @Charles White's write up at http://www2.hawaii.edu/~whitece6/posts/firstpost/ on an issue with the current transistor models (possibly related to bin models)?

This has nothing to do with model binning, it's just that the models are completely broken at low inversion levels, likely due to bad population of the BSIM model parameters. I made a post on this 1+ year ago and really hope that we can get better models released soon. Designing low-power analog circuits with these models is like playing the lottery.