Hello. I'm preparing a presentation for the SSCS chipathon on Latchup. I would like to provide a reference to the layout rules document to point out latchup-related layout rules (like max distance from MOS diffusion to well/substrate tap). I did a search in the threads and found a copy of 'SkyWater SKY130 Design Rules.odt' attached to a thread. Where is the source for this document? (SkyWater or EFabless website?) I'd like to refer people to an online copy rather than sending around a copy of this document. Thanks for your help.

Could be this? https://antmicro-skywater-pdk-docs.readthedocs.io/en/latest/rules.html

Thanks Boris. It appears to have all the minimum design rules and a lot of useful reference info. Maybe I'm missing it, but I don't see a maximum diffusion to tap spacing or other latchup-related guidelines for IOs.

Looks like 6um is recommended but 15um is permitted with

81/14

.

6um tap to diff rule will not be checked in this regionnDiffusion >6u from related tap, requiring >50u from sigPadDiff && sigPadMetNtr).nShould be used sparingly and only over the portion of the layout to remove DRC violations. This layer is not to be used if a tapping solution can be found. This layer can only be used if there is low risk for latchup. This layer will be reviewed during PDQC.

Looks like magic drc only checks for 15um, though. https://skywater-pdk.readthedocs.io/en/main/rules/layers.html

Thanks Mitch. Do you know of any explicit documentation of the 6um tap to diff rule?

Just what I quoted above.