hi, simulation gets stuck during the power calculation phase while I tried to harden the user project. what could be the reason?

set ::env(STA_REPORT_POWER) 0

Update this in config.tcl and try

I modified the config file of user project. But the problem persists. And the problem is with the project I have created, not the example caravel user project

have you defined right

CLOCK_PORT

?

I used wishbone clock. so I didnt modify clock_port in the config file

without test case its difficult point out reason