What's going on with the analog pins here? Trying to figure out what's going on with ESD.

This is one of three connections to pads that I custom altered to carry as much current as I could get them to, so they could be useful for high(er)-power analog projects. The signal pins are triple layered on metals 3, 4, and,5. The inner pins are connections to a (3.3V) voltage clamp. They are otherwise unconnected. If you want the voltage clamp for ESD protection, then connect the positive clamp pin to a power supply and the negative clamp pin to a ground supply, with wires as large as you can make them, practically. The connection is never going to be as good as it really ought to be for a clamp, but it's a lot better than nothing.

My design isn't particularly high power. I'm just trying to understand what I need to do so that my chip doesn't blow up from ESD as soon as I touch it. And also where to get ground, 1.8V and 3.3V from. So if I understand you correctly, I should use these pins as power and ground, but for my other IOs I need to add custom protection? Looking at the device details I'm not super clear about how to actually use the ESD fets. This random image on google suggests I just tie them between the input and ground. I thought maybe they have a really high threshold voltage so they conduct at high voltage, but looks like you're supposed to tie the gate to ground. I guess the secret is in the N-well under the drain? https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#nmos-esd-fet

Yes; if you do not have any special needs for the power supply like high current or voltage outside of the range 0 to 5.5V, then you should just use the available user power supplies

vdda1

,

vdda2

,

vccd1

, and

vccd2

. These supplies are all independent and already properly clamped and ESD protected.

@Tim Edwards Please confirm following interpretation for clarity on connections to

user_analog[6:4

] pads: Pads`user_analog[6:4]` are to be used if supply voltage other than

1.8V

or

3.3V

are required in the chip. Or if requirement is to supply large current from 1.8V or 3.3V supply voltages (which might not be possible from

vdda1/vdda2

and

vccd1/vccd2

digital power pads). In order to provide return path to ESD current through power clamp ckt ,

io_clamp_high

and

io_clamp_low

connections in

user_analog[6:4]

pads should be connected to the same supply and ground voltages as supplied to chip through these pads.