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Mostly power related question but posting here for...
# analog-design
w
Mostly power related question but posting here for greater visibility: When you have something like a PMOS/NMOS output buffer and have reverse current it seems close to impossible to have the body diode conduct if the gate threshold is much less than a diode drop?
If you apply a voltage higher than the supply rail / lower than ground to the buffer output it brings the drain of the mosfet above the source. the MOSFET is symmetrical, so thats the same as a positive voltage on the gate. If the FET does not turn on the drain to well body diode will conduct.
But if the gate threshold is low you have a positive gate voltage and the FET seems like it should turn on.
Given that the NMOS devices can be isolated with a deep nwell it seems it should be possible to make a clamping structure that does not have any diode conduction this way using the native NMOS FET.
t
@Weston Braun: I don't get that. Your nFET device bulk still has to be held at or below the minimum of (drain, source) voltage to keep it from forward-biasing into either one of the source or drain. You can't hold the bulk at the drain voltage or else it will forward bias into the source under normal operating conditions. So the bulk has to be held at the source voltage (nominally ground), and applying a sufficiently negative voltage to the drain is always going to forward bias the bulk-to-drain junction.
w
@Tim Edwards aside from the FET bulk connection drain and source are interchangeable. if I tie the gate to the source and then apply a negative voltage to the drain that should turn the FET on, as the source is now effectively the drain and the gate is tied to what is now the drain. If the turn on threshold of the FET is less than a diode drop the FET will conduct current through its channel before the bulk to drain junction can conduct. Unless the bulk bias significantly modulates the turn on voltage threshold?
At some point the V/I curves of a FET with its gate tied to drain and the bulk to drain junction will intersect and the diode will conduct significant current. But for a FET where the threshold is << than the bandgap of the diode junction the FET should conduct significant currents before the diode conducts.
This should hold for the 20V NMOS zero-VT FET and all the native doped NMOS, which have threshold voltages << 0.7V
Looking at the simulation models it seems that bulk bias is modulating the transconductance, but you can see that the nfet_20v0_zvt device conducts in the reverse direction while the nfet_20v0 device only does when the body diode starts conducting
Sorry, those plots are wrong. Correct plots and schematic:
Screenshot from 2022-06-28 16-52-08.png,Screenshot from 2022-06-28 16-52-16.png
So the transistor acts as a diode with conduction voltage less than a diode drop.
And no carriers are injected due to reverse conduction of the body diode
l
Where is the bulk terminal connected? Is it floating?
Ok, First, the standard MOSFET is symmetrical, but not the 20 V ones. See, they are asymmetrical.
There is diode between the drain and the bulk terminals, and also between the source and bulk terminals. The simulator tries to attribute a voltage to it, but it is not realistic, as the bulk terminal will always be connected to some voltage potential. And there is a default gmin between each terminal that is greater than the actual conductance of the reverse biased diodes. Those simulations are not accurate at all.
But, yes, you can have a transistor with such a small VT, that, if you short the gate and bulk terminals, there will be a higher drain current as result of VGS than a parasitic substract current due to forward-body-biasing (VBS > 0). This is the so called dynamic threshold voltage MOSFET technique. (https://ieeexplore.ieee.org/abstract/document/383301)
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