Can I expect ngspice to simulate reverse recovery ...
# analog-designw
Weston Braun
06/23/2022, 8:03 AMCan I expect ngspice to simulate reverse recovery for diodes on SKY130? I am having problems with the diode models, but using the mosfet body - drain connection as a diode I do not seem to be observing any reverse recovery delay or charge.
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Weston Braun
06/23/2022, 8:32 AMI managed to get the normal diode models working, the area scaling was off. I am still not seeing anything I would consider reverse recovery charge, simulating down to sub 0.1ns timestep.
Weston Braun
06/23/2022, 8:33 AMI was under the impression that the parasitic diodes should be quite slow, am I mistaken? I am not sure what to expect from the PDK in this regard
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yrrapt
06/23/2022, 5:10 PMIn a bulk process like sky130 you shouldn't forward bias the body diodes or you can induce latchup. That's why they're not modeled well in the forward direction
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Weston Braun
06/23/2022, 5:30 PMYou can isolate the NMOS with the deep N Well.
Weston Braun
06/23/2022, 5:30 PMI am not planning on running it as a diode, but in switching converters it can happen and I want to be able to model what will happen
Weston Braun
06/23/2022, 5:31 PMAlso, none of the diode models seem to be exhibiting reverse recovery loss. Or are they just a lot faster than I am expecting?
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yrrapt
06/23/2022, 6:26 PMAt the minimum you're still going to have a parasitic bipolar created between DNWELL and NMOS D/S if the body diode conducts. That won't be modelled. There may also be a thyristor structure hiding in there.
My point being that it's unmodelled because its not normally a recommended operating condition. If it was me, I'd be more tempted to try and prevent the diode conduction than trying to simulate what happens when it does.
You can also just look at the diode spice models and see what effects are included
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Weston Braun
06/23/2022, 6:46 PMIf you connect the DNWELL to VSS the parasitic bipolar is effectively shorted
Weston Braun
06/23/2022, 6:47 PMIn some cases its impossible to fully prevent the body diode from conducting. Such as if an ESD protection structure conducts. Or there is slight deadtime in a switching converter, which you need to some extent to prevent shootthrough of the power stage.
Weston Braun
06/23/2022, 6:51 PMI assume that for commercial ICs they model these things, so I am just a bit confused that the spice models seem to be missing it
Weston Braun
06/23/2022, 6:53 PMfrom the ngspice manual
Copy code
Charge storage effects are modeled by a transit time, tt, and
a nonlinear depletion layer capacitance that is determined by the parameters cjo, vj,
and my
yrrapt
06/23/2022, 7:00 PMOk yeah, that's a nice trick, I haven't seen that before
yrrapt
06/23/2022, 7:03 PMFor some processes with a focus on mixed signal/power that probably is modelled but I would expect it's with a separate device, not the built-in diodes in each FET.
I've worked in processes that have 6 terminal FETs for the wells and another one has two separate diodes placed in the schematic that get extracted areas from PEX.
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Weston Braun
06/23/2022, 7:15 PMI am having trouble finding full documentation on the spice level 3 diode model. But it looks like the ttt1 and ttt2 parameters I was seeing in the diode models are not revovery time related. its still just tt.
Weston Braun
06/23/2022, 7:16 PMWhich seems to not be defined in any of the diode models 😕
Weston Braun
06/23/2022, 7:17 PMI guess I can just try to measure it from the power stage on the chip I taped out
Weston Braun
06/23/2022, 7:17 PMRight now I have external shottkey diodes on my power stage. Working up the courage to remove them (and hopefully not have anything blow up)
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