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# ieee-sscs-dc-22
m
Soft connection checks: Looks like there are multiple psubstrate and nwell taps not connected to power through metal.
SSCS-22-1-2.png
SSCS-22-1-3.png,SSCS-22-1-4.png
The netlist at 
netgen/user_analog_project_wrapper.spice
contains the extracted version of 
TOPf_flatten
which is meaningless for LVS. Is the schematic version available? The powered gate level verilog for 
user_proj_systollic
is also missing.
TOPf5
clkbuf
missing taps. Also, nmos and pmos mos both connected to vccd.
a
Let me upload the schematic version of the top. The reason why powered netlist is not there. In our case, there are three projects on a single chip 2 projects are analog and 1 is digital. After doing the top layout simulation of a digital project, I just places the digital project GDS in the analog wrapper and connected them with the board manually Let me upload the powered netlist on GitHub repository
👍 1
We did the post layout simulation of matrix multiplier, it works fine.
m
Looks like 
wbs_dat_i[27]
is not connected.
SSCS-22-1-wbs.png
Post layout simulation won’t reflect soft connection errors.
a
Thanks @Mitch Bailey Let me check and update you.
@Mitch Bailey the multiple wells are short together and hence they are connected to each other. So, the connection is made through shorting and without using metal layers. Thanks
m
Exactly. Because of the high resistivity of the well/substrate, this is generally avoided. Also power is generally supplied by metal layers rather than 
li
.
a
Yes, you are right that makes sense. I will update to DC-DC team.
👍 1
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