Is there a way to flatten the netlist without losi...
# magic
c
Is there a way to flatten the netlist without losing the labels while getting rid of subcircuits? I am trying to extract the netlist of circuit that is made of up of four components that I had previously created. However, when I flatten the netlist, I lose the labels that are the top cell (and the connections it seems like), and I'm left with only the labels in the subcircuits.
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X24 22_DCxtalFlatten_0/vin 22_DCxtalFlatten_0/kin 22_DCxtalFlatten_0/vp w_1692_176# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.3e+07u l=150000u
X25 22_DCxtalFlatten_0/vp 22_DCxtalFlatten_0/k3 22_DCxtalFlatten_0/gnd a_n6337_916# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.3e+07u l=150000u
X26 22_FO4Flatten_1/in2 22_FO4Flatten_1/in 22_FO4Flatten_0/vdd w_n6373_16636# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X27 22_FO4Flatten_1/in4 22_FO4Flatten_1/in3 22_DCxtalFlatten_0/gnd a_n6337_916# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.6e+07u l=150000u
X28 22_FO4Flatten_2/in4 22_FO4Flatten_2/in3 22_DCxtalFlatten_0/gnd a_n6337_916# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.6e+07u l=150000u
When I don't flatten the netlist, I still preserve the top most labels (and therefore connections), but if I try to extract it with parasitics, then I get subcircuits with incorrect nodes.
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X24 vpf k3f gnd VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.3e+07u l=150000u
X25 voutf koutf vpf 22_DCxtalFlatten_0/w_800_14000# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.3e+07u l=150000u
X26 vpf koutf voutf 22_DCxtalFlatten_0/w_1600_14000# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.3e+07u l=150000u
X27 gnd k3f vpf VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.3e+07u l=150000u
X28 vinf kinf vpf 22_DCxtalFlatten_0/w_0_0# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u
Is there any fix to get around this?
m
Was there a writeup of the parasitic extraction flow so we don’t have to repeat these discussions? @Tim Edwards Here’s a discussion on flattening. https://open-source-silicon.slack.com/archives/C016YSAP6TZ/p1645029098733729?thread_ts=1644998694.479219&cid=C016YSAP6TZ
t
I'm not sure why it would be preferring the hierarchical label over the top level label; it's not supposed to do that. You can try flattening with the
-dotoplabels
option.
c
@Tim Edwards Hi Tim, I tried using the -dotoplabels option, but it seems to have the same result. Is there any way to fix the subcircuits to have the correct terminals without flattening it? I'm using Magic 8.30 version 290, but I'm not sure if need to update it? Thanks!
t
Try updating magic first. Your version is from April, and quite a few revisions behind the current version.
👍 1
c
Okay, thanks!