For Varactor, Xschem has three port (as attached). In magic its a PMOS. So, to make right connection in layout, which part of PMOS will be b, c0, c1 like in schematic? Thanks in advance!

@Mohammad Farhan I believe source and drain of the pmos will be shorted together and become

c1

, the Nwell ring will be

b

and gate terminals will become

c0

@Mohammad Farhan: The layout is not a pMOS; the layout of a varactor is created from n-diffusion (n-tap) in n-well. The source and drain are shorted together and shorted to the nwell. So the poly gate is

c0

and the source-drain-well node is

c1

and the substrate guard ring is

b

.

Hello, I have a top-level question for Tim: There are 14 varactor test files among the CoolCAD tests https://github.com/google/skywater-pdk-sky130-raw-data/tree/main/sky130_fd_pr/cells/unsorted/cap_var/CV. The question is: Were the test circuits created with Magic using the command Devices 1 --> MOS varactor and filling out the dialog box? To elaborate: I made an Excel graph of the 14 traces (see image). While detail is low in the image, notice that some traces cross, some traces have kinks just left of the center, and there is some inconsistent breakdown on the left. In examining the graphs in detail, there are two types of curves based on whether there is a “_D2” in the file name. The ones without _D2 look like they have two terminals tied together. The ones with _D2 have substantially higher ratio of capacitance change (>10:1 and identifiable by the kink). In the literature, the higher ratio is the result of using the third terminal as an additional control. However, I have not figured out how the _D2 in the file name adds the additional control. I'm trying to figure out how to design varactors like the ones CoolCAD tested.

@Erik DeBenedictis: They're from the SkyWater test structure tiles. You can find a name correspondence in this document: https://github.com/google/skywater-pdk-sky130-raw-data/blob/main/docs/sky130-testtile-proprietary/sky130-testtile-pad-documentation.pdf For example, the first dataset in the directory listing on github is

varactor_w40_l40_m1(3316_2_3).mdm

. The "w40_l40_m1" refers to the device width and length and number of devices in parallel; the

3316

is a test structure number and corresponds to the table entry in the PDF linked above; you can see that

3316

is a set of five varactor tests. The

2

and

3

are the pins that were probed in the test, and you can see from the table that those two pins connect to the first of the five varactors, which is the 40x40 one, so it all checks out! Beyond that, I don't think the

_D2

means anything other than the measurement probably (?) comes from the 2nd test structure tile. I can't find any information on it, so it could just as well be a different reticle or different test run. The curves are all very standard for a varactor; there are only two pins defined (one is the gate; the other is the source/drain/bulk, all shorted together). A varactor has two main modes of operation in accumulation and in inversion which are relatively flat, with a transition region in between.

Hello Tim: I’m making the argument that there are dozens of varactor types and that various Slack thread authors are implicitly assuming different types. For this open source initiative to design with varactors, we need to know what varactor type is in the Sky130 PDK. Is it allowable under the NDA with SkyWater for somebody to look at the layout behind the CoolCAD measurement and report which model it is? I am attaching an image of the first two CoolCAD test files and the Excel file that generated the image. The two curves have fundamentally different shapes, but they are measured from what documentation says are the same layout but with different threshold voltages (see https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#v-accumulation-mode-mos-varactors for term equivalence, noting xcnwvc2 and xcnwvc in the black images with the varactor symbol). The curves that appear in Slack are derived from the Spice model that has an equation based on hyperbolics (tanh) and looks most like the top curve in the image. The smooth curve with hyperbolics is for a reverse-biased capacitor, yet, Tim, you are talking about readout through the gate terminal of a “half-MOSFET.” The dissonant information is the bottom curve in the image, which has a bigger capacitance ratio and a kink. I can’t exactly say what is going on because I only know the layout built into Magic and not the one used by SkyWater, but I can offer a hypothesis that may be in the correct direction. I’m guessing the varactor in Magic/Sky130 is similar to the one in https://repository.hkust.edu.hk/ir/bitstream/1783.1-2160/1/1_2wide.pdf (a paper available from IEEE, but the link is not paywalled). The paper is about a 3-terminal varactor. How can we explain the differences in the curves in the attached image? If you look at Fig. 3 in the IEEE paper, the authors are able to increase the capacitance ratio by applying a bias voltage to the insulated gate. Switching a circuit between an hvt and an lvt transistor is equivalent to installing a voltage source of value hvt-lvt in series with the insulated gate -- exactly the position of the bias voltage in the IEEE paper. If the measured chip has the varactor in the IEEE paper, CoolCAD did measurements with two values of the bias voltage and we observe that it changes the capacitance ratio.

@Erik DeBenedictis: There are only two varactor types defined (modeled) in sky130, and those are listed in the test document (

cap_var_hvt

and

cap_var_lvt

) for each of the test devices. From the table at https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#v-accumulation-mode-mos-varactors, these should have approximately the same capacitance in accumulation and inversion modes, and should differ mainly in the threshold position. I can't speak for the methodology used for the measurements; it's very difficult to directly measure capacitance of a device using a probe. A better way is to use the device to control a VCO, measure the VCO frequency, and infer the capacitance. For that you have to have the proper circuit setup on chip.

I suspect CoolCAD forgot to hook up ground; but in any event, we may be approaching the end of what we can resolve until there is more information. The top of the test files from CoolCAD have the machine setup. The spreadsheet says varactor tests should have 3 pins: Psub, WELL, and GATE. However, the machine setup section in the files I graphed only deals with two pins. I checked and the MiM capacitor section nearby has the same setup as a varactor.