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<@U016HSAA3RQ> <@U016EM8L91B> I'm rerunning gate l...
# caravel
a
@jeffdi @Tim Edwards I'm rerunning gate level simulation for the updated Microwatt MPW7 submission. I might have missed something recent, but 
make gpio_defaults
from the 
caravel_user_project
directory doesn't seem to do the right thing. Ultimately it needs to make modifications to 
caravel/verilog/gl/caravel.v
but the script is looking for it in the wrong spot:
Copy code
vpath = user_project_path + '/verilog'
    glpath = vpath + '/gl'
This seems to fix it for me, but is it what was intended?
Copy code
--- a/scripts/gen_gpio_defaults.py
+++ b/scripts/gen_gpio_defaults.py
@@ -120,16 +120,16 @@ if __name__ == '__main__':
         print('Error:  Project path "' + user_project_path + '" does not exist or is not readable.')
         sys.exit(1)
 
-    magpath = user_project_path + '/mag'
-    vpath = user_project_path + '/verilog'
-    glpath = vpath + '/gl'
-
     try:
         caravel_path = os.environ['CARAVEL_ROOT']
     except:
         print('Warning:  CARAVEL_ROOT not set;  assuming the cwd.')
         caravel_path = os.getcwd()
 
+    magpath = caravel_path + '/mag'
+    vpath = caravel_path + '/verilog'
+    glpath = vpath + '/gl'
+
     # Check paths
     if not os.path.isdir(vpath):
         print('No directory ' + vpath + ' found (path to verilog).')
@@ -145,7 +145,7 @@ if __name__ == '__main__':
 
     # Parse the user defines verilog file
     kvpairs = {}
-    user_defines_path = vpath + '/rtl/user_defines.v'
+    user_defines_path = user_project_path + '/verilog/rtl/user_defines.v'
     if not os.path.isfile(user_defines_path):
         user_defines_path = caravel_path + '/verilog/rtl/user_defines.v'
m
@Anton Blanchard 
caravel/verilog/gl/caravel.v
is the master version and is not supposed to change. When make gpio_defaults is run, 
caravel/verilog/gl/caravel.v
is read and modified with the correct gpio defaults (from the users 
verilog/rtl/user_defines.v
which is required in precheck as of mpw7) and then written to 
verilog/gl/caravel.v
a
Thanks @Mitch Bailey, let me undo that patch. The issue is then in 
./mgmt_core_wrapper/verilog/includes/includes.gl.caravel
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-v $(CARAVEL_PATH)/gl/caravel.v
It's hardwired to point to the caravel version. I could replicate the whole file in my project and modify it, but that would be a shame
That also explains why this was working on the first MPW7 submission - we were using include directories and not explicit paths to every verilog file. That allowed either version to be used.
t
I have no problem with modifying the script to work for the end user, as long as the solution still works for the final chip assembly process.
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