Hi, @Micah Tseng your questions all make very good sense, so I will go thru all the questions and come back on this soon. For bussing the syntax

D[1..3]

is one of the possible syntaxes, and it expands to

D1,D2,D3

, However if you use

D[1:3]

it expands to

D[1],D[2],D[3]

. This latter notation is OK for spice and Verilog. I wil certainly add an option to have more Openlane friendly verilog netlists. Some things can already be done, some others probably require little changes in the program.

@Stefan Schippers Thank you! That’s awesome! I tried using

D[1:3]

with ngspice and it wasn’t happy with it….I might have done something wrong though. When I switch to

D[1..3]

it worked fine.

the '[..]' is a problem with ngspice only if you are also using XSPICE primitives. In this case you can add a

netlist_options.sym

component to instruct xschem to replace

[

and

]

with two different characters (

x

and

x

in the example):

Oh, that’s excellent information!

for a normal ngspice transistor level simulation I have a complete example of a ROM cell simulated with ngspice, this schematic is full of busses:

Ah, that’s cool.

when generating netlists for various backend simulators there are lot of different rules for nets, instance names and identifiers, also different spice simulators have different syntax conventions, so I add syntax options where needed, since there is no one fits all solution.

That makes sense. I didn’t know about this

netlist_options.sym

but it would have saved a ton of headache.

For the openlane-friendly verilog netlist will come to some solution tomorrow I hope 🙂

Oh, take your time! There’s no rush.

@Micah Tseng I have updated both xschem and xschem_sky130, I have added a '`verilogprefix`' attribute to all standard cells, so they will be netlisted in verilog with the prefix as you requested. Xschem will use this attribute if found in the symbol: You have shown xschem netlisting the power pins for the standard cells, this is already fixed in recent versions of xschem, see

extra

and

verilog_extra

attribute description in the manual.

TL;DR: 
if VGND, VPWR, VPB, VNB are not listed in symbol verilog_extra attribute they will not be netlisted.
if VGND, VPWR, VPB, VNB, prefix are listed in symbol extra attribute they will NOT be netlisted as instance parameters.

Now a nand standard cell will be netlisted as:

sky130_fd_sc_hd__nand2_1
x1 ( 
 .A( A ),
 .B( B ),
 .Y( IX )
);

@Stefan Schippers This is awesome! You rock!