Hello @Stefan Schippers, I was wondering if perhaps we could discuss a feature request for xschem? For my SAR ADC, I used what is evidently a new workflow that hasn’t been used before with the Sky130 PDK. I wanted to ensure accurate and tight timing for my controller so I chose to design my digital logic in Xschem to utilize spice simulations and then I took the structural verilog netlist from Xschem and pushed it into OpenLane bypassing the synthesis stage. It worked, but the workflow was rough. I’ve already discussed a bunch with the OpenLane crew (https://github.com/The-OpenROAD-Project/OpenLane/issues/1420) since it exposed a bug or two in Openlane which have been patched, but the Xschem side was also a little rough and I would LOVE your thoughts. I think this workflow has some value for mixed signal designs where the timing requirements are stringent and require precise timing or the digital portions are a little too small for writing behavioral verilog, but a little too large to want to layout the standard cells by hand. ISSUES Verilog There are two issues with the verilog outputted from Xschem for OpenLane: Parameters and the full pathing. I think the parameters might have changed in a recent Xschem update, but here is what I had to do for my xschem version. Xschem outputs an instantiation of a standard cell as:

and2_0
#(
.VGND ( VSS ) ,
.VNB ( VSS ) ,
.VPB ( VDD ) ,
.VPWR ( VDD ) ,
.prefix ( sky130_fd_sc_hd__ )
)
x2 ( 
 .A( S ),
 .B( IN ),
 .X( OUT_1 )
);

However, OpenLane expects an instantiation to look like

sky130_fd_sc_hd__and2_0 x2 ( 
 .A( S ),
 .B( IN ),
 .X( OUT_1 )
);

So I wrote a python script to handle removing the parameters and inserting the full name of the standard cell. You can find the script here: https://github.com/UAH-IC-Design-Team/sky130-10-bit-SAR-ADC/blob/dev/util/verilog_parameter_strip.py Bussing: Since I ran simulations in Spice, I used the Xschem spice bussing notation:

net_name[1..10]

rather than the verilog bussing

net_name[1:10]

. It worked well for simulating thing, but converting that in the netlist to verilog acceptable bussing in python turned into a nightmare and I ended up simply redoing all the schematics to remove bussing entirely. FEATURES 1. Verilog: What do you think about adding a checkbox that would modify the netlist generation and strip the parameters and insert the full name of the of the cell? 2. Bussing: This one is harder, but it would be nice to have a way to use busses, but still be able to output both spice and verilog netlists. Like perhaps, always inputing verilog busses in the schematic, but there is a checkbox to convert the busses to spice busses on the netlist generation? I’m not sure on this one what is the best/easiest, but it would be nice for this workflow and also would also easily allow both spice and event based simulations for thorough design verification. I am a little strapped for time until the semester finishes, but if I can help out in anyway, let me know.