Hmm. Unfortunately, my suggestion doesn’t appear to work like I hoped it would. So here’s the schematic and symbol created.

sar_schematic.png,sar_symbol.png

And here’s how I edited the

sym

file (sorted the lines below

T {@name}

and rearranged the

B

lines to match the verilog port order.

v {xschem version=3.0.0 file_version=1.2}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
T {@symname} -220.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -82 0 0 0.2 0.2 {}
B 5 -152.5 -62.5 -147.5 -57.5 {name=clk dir=in }
B 5 -152.5 -42.5 -147.5 -37.5 {name=ADClk dir=in }
B 5 -152.5 -22.5 -147.5 -17.5 {name=DelayClk dir=in }
B 5 -152.5 -2.5 -147.5 2.5 {name=ADRst dir=in }
B 5 147.5 -42.5 152.5 -37.5 {name=Sample dir=out }
B 5 147.5 -62.5 152.5 -57.5 {name=Value[9:0] dir=out }
B 5 -152.5 17.5 -147.5 22.5 {name=CMP dir=in }
B 5 -152.5 37.5 -147.5 42.5 {name=Sin dir=in }
B 5 147.5 -22.5 152.5 -17.5 {name=Sout dir=out }
B 5 -152.5 57.5 -147.5 62.5 {name=Mode dir=in }
B 5 147.5 -2.5 152.5 2.5 {name=VPWR dir=inout }
B 5 147.5 17.5 152.5 22.5 {name=VGND dir=inout }
L 4 -130 -70 -130 70 {}
L 4 -130 -70 130 -70 {}
L 4 -130 70 130 70 {}
L 4 -150 -20 -130 -20 {}
L 4 -150 -40 -130 -40 {}
L 4 -150 -60 -130 -60 {}
L 4 -150 0 -130 0 {}
L 4 -150 20 -130 20 {}
L 4 -150 40 -130 40 {}
L 4 -150 60 -130 60 {}
L 4 130 -20 150 -20 {}
L 4 130 -40 150 -40 {}
L 4 130 -60 150 -60 {}
L 4 130 -70 130 70 {}
L 7 130 0 150 0 {}
L 7 130 20 150 20 {}
T {ADClk} -125 -44 0 0 0.2 0.2 {}
T {ADRst} -125 -4 0 0 0.2 0.2 {}
T {CMP} -125 16 0 0 0.2 0.2 {}
T {DelayClk} -125 -24 0 0 0.2 0.2 {}
T {Mode} -125 56 0 0 0.2 0.2 {}
T {Sample} 125 -44 0 1 0.2 0.2 {}
T {Sin} -125 36 0 0 0.2 0.2 {}
T {Sout} 125 -24 0 1 0.2 0.2 {}
T {VGND} 125 16 0 1 0.2 0.2 {}
T {VPWR} 125 -4 0 1 0.2 0.2 {}
T {Value[9:0]} 125 -64 0 1 0.2 0.2 {}
T {clk} -125 -64 0 0 0.2 0.2 {}

Hi, I followed your instruction and then, opened the .sym file and rearrange the pins. The created digital block just contains the pins, not the schematic. How I can do a simulation to test my SARADC? The Verilog code should be imported into this block, the same as we do in cadence. But, I don't know how I can do it. Thanks.