@Abhinav Uppal: For one, you're not going to get a logic analyzer output to run at 40MHz, since that's the core clock rate, and you can only drive a logic analyzer output by setting it in software, which implies a maximum rate of 20MHz, and in practice much lower, since your program will have to loop through some code, executing other instructions as well. Ignoring that detail, though, if you are driving only output from the logic analyzer into your project, then you only care about the timing of clock vs. select, where both are changing on the same core clock cycle, and presumably travel a similar path to get to the user project. And STA isn't going to tell you anything useful unless you can either make a liberty file representing your comparator controls, or if those controls are made with standard cells, you could mock up just the digital part and check that the signals switch with sufficient margin. But all that is kind of beside the point, anyway, since we don't have any known good timing for the sky130B variant, so if you got an STA result, it wouldn't necessarily be accurate.