@Tim Edwards @mshalan: @FatsieFS has ported his 3.3v std cell library to GF180. We'd like to test it out on the dec 5th run. The question is: can we run the caravel at 3.3v?

We only have IP for 5V, and the operating spec for the I/O has a stated minimum voltage of 4.5V.

@mehdi @Tim Edwards Could we design some level shifters to allow this?

level shifter can be used for upper conversion. We can provide some feedback on how to design them if we know what is the spec. (speed, voltages etc..).

How hard would a 100Mhz ish 3.3V --> 5V thing be that could be auto placed by OpenROAD (i.e. standard cell form factor)?

Depending on the Shifter you use. If you have no power limitation constraints, this should be fairly easy. @woobean has designed a split level converter for the sensors in Intel 16nm. So I can assign him this after the tapeout is over.

Cool! Let me know if there's any thing I can help with

Sure, I will ask my student to work on that after the 16nm tapeout this week.

Well noted.

The issue here is that currently there is literally no way to get a 3.3V power line into the chip. You would have to design not only a level shifter, but also a 3.3V generating LDO, and then maybe an ADC so that you can check whether the LDO is working or not. The only other solution is for us to march ahead and develop the "caravan" analog version of the chip for GF180MCU. That is currently not planned for the 1st MPW, but we also have an obligation to fill the first MPW run, so if that's not happening because we're not offering any ability to use 3.3V circuitry, then offering a "caravan" padframe for GF180MCU could get boosted up to a critical requirement.

We’re having a think about what we can do here. Also chatting with the gf folk

@Rob Taylor: Yes, but we could provide bare analog pads, which have the basic reverse-biased diodes to power and ground, which would suffice with plenty of decap and careful handling.

That could be very helpful! @FatsieFS what do you think?

We could do an IO ring inside the IO ring. But then the problem moves to packaging. If the wafer gets RDL processing and bumping we won't be able to package it.

I do not think we are going to do WLCSP again. We really desperately need 3.3V IP for this process, so if you deliver the design, I'm sure we can find some way to get you bare dies.

@Tim Edwards Good to know about WLCSP. Will use the info for furthering the design.

@FatsieFS: I am not entirely certain about this. So far nobody has mentioned WLCSP on the GF process so I assumed that we would not do it. But it might get forced on us anyway.

@proppy Just to loop you in on the above

I think the plan is still to do wlcsp.