It seems that openlane can manage some SV constructs like genvar for synthesis, but if the same file is used for blackboxing, the flow will fail. Has anyone else noticed this?

Yes, I have noticed the same behaviour. I then resorted to the GL representation of the module for the blackbox.

I tried that but it failed with power supply issues

I'm not sure it has something to do with SV (you mean SystemVerilog ?) as genvar is already in Verilog, so yosys understands it. It looks as if an additional OL parser has an issue with the Verilog genvar construct.

Here is the link to the repo: https://github.com/semify-eda/caravel_wfg And in particular the configuration of the user_project_wrapper, where the blackbox files are defined: https://github.com/semify-eda/caravel_wfg/blob/wfg-mpw-7/openlane/user_project_wrapper/config.tcl