We are trying to run the final precheck. There is a consistency error at step 5 of 13 we are getting right now. I also updated the README.md file according to @mehdi's tutorial session. What am I missing here?

@omla: Please see the above error (python exception and traceback) coming from the precheck system.

Hey @Tim Edwards and @omla, we would like to hear something from you if there is any solution found for this specific problems. We tried several times. But nothing changed. Each time we are getting this consistency error.

@jeffdi: Is there someone with platform precheck access who can help with this?

Hello, sorry for the lack of response previously, we are aware of this issue and we are hoping to release a fix soon, just to confirm your projects are

analog

projects @Mohammad Farhan @Andalib Nizam ?

@omla, yes, our project is fully analog. I just ran the precheck again with newly generated gds, spice files. The consistency error has this details:

[11/21/22 13:57:14 PST] PARSING LAYOUT FAILED

The user_analog_project_wrapper layout fails parsing because: Top module: user_analog_project_wrapper is not found in sscs_pico_chip_7/gds/user_analog_project_wrapper.gds.

I am pasting the full log here just for your reference:

[11/21/22 13:53:07 PST] SUBMITTED
                

        
    
        
            


            [11/21/22 13:57:06 PST] STARTED
                

        
    
        
            


            [11/21/22 13:57:08 PST] PROJECT GIT INFO
                Repository: <https://github.com/AndalibN/Electrochemical-Water-Quality-Monitoring.git> | Branch: main | Commit: 0845907eb5d096cbb6aba154208b76c1cb29e0ab

        
    
        
            


            [11/21/22 13:57:08 PST] EXTRACTING FILES
                Extracting compressed files in: sscs_pico_chip_7

        
    
        
            


            [11/21/22 13:57:08 PST] PROJECT TYPE INFO
                analog

        
    
        
            


            [11/21/22 13:57:08 PST] PROJECT GDS INFO
                user_analog_project_wrapper: 1a1c40e8fa1620af5de54d3e028b40ea2418d594

        
    
        
            


            [11/21/22 13:57:08 PST] TOOLS INFO
                KLayout: v0.27.12 | Magic: v8.3.340

        
    
        
            


            [11/21/22 13:57:08 PST] PDKS INFO
                SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f

        
    
        
            


            [11/21/22 13:57:08 PST] START
                Precheck Started, the full log 'precheck.log' will be located in 'sscs_pico_chip_7/jobs/mpw_precheck/32ffaafb-f70d-4398-9b3a-ecc0762a6d42/logs'

        
    
        
            


            [11/21/22 13:57:08 PST] PRECHECK SEQUENCE
                Precheck will run the following checks: [Makefile, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]

        
    
        
            


            [11/21/22 13:57:08 PST] STEP UPDATE
                Executing Check 1 of 11: Makefile

        
    
        
            


            [11/21/22 13:57:09 PST] MAKEFILE CHECK PASSED
                Makefile valid.

        
    
        
            


            [11/21/22 13:57:09 PST] STEP UPDATE
                Executing Check 2 of 11: Consistency

        
    
        
            


            [11/21/22 13:57:14 PST] PARSING LAYOUT FAILED
                The user_analog_project_wrapper layout fails parsing because: Top module: user_analog_project_wrapper is not found in sscs_pico_chip_7/gds/user_analog_project_wrapper.gds.

        
    
        
            


            [11/21/22 13:57:14 PST] CONSISTENCY CHECK FAILED
                The user netlist and the top netlist are not valid.

        
    
        
            


            [11/21/22 13:57:14 PST] STEP UPDATE
                Executing Check 3 of 11: GPIO-Defines

        
    
        
            


            [11/21/22 13:57:16 PST] GPIO-DEFINES CHECK PASSED
                The user verilog/rtl/user_defines.v is valid.

        
    
        
            


            [11/21/22 13:57:16 PST] STEP UPDATE
                Executing Check 4 of 11: XOR

        
    
        
            


            [11/21/22 13:57:17 PST] XOR CHECK FAILED
                The GDS file has non-conforming geometries.

        
    
        
            


            [11/21/22 13:57:17 PST] STEP UPDATE
                Executing Check 5 of 11: Magic DRC

        
    
        
            


            [11/21/22 13:57:18 PST] MAGIC DRC CHECK PASSED
                The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

        
    
        
            


            [11/21/22 13:57:18 PST] STEP UPDATE
                Executing Check 6 of 11: Klayout FEOL

        
    
        
            


            [11/21/22 13:57:23 PST] KLAYOUT FEOL CHECK FAILED
                The GDS file, user_analog_project_wrapper.gds, has DRC violations.

        
    
        
            


            [11/21/22 13:57:23 PST] STEP UPDATE
                Executing Check 7 of 11: Klayout BEOL

        
    
        
            


            [11/21/22 13:57:42 PST] KLAYOUT BEOL CHECK FAILED
                The GDS file, user_analog_project_wrapper.gds, has DRC violations.

        
    
        
            


            [11/21/22 13:57:42 PST] STEP UPDATE
                Executing Check 8 of 11: Klayout Offgrid

        
    
        
            


            [11/21/22 13:57:48 PST] KLAYOUT OFFGRID CHECK PASSED
                The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

        
    
        
            


            [11/21/22 13:57:48 PST] STEP UPDATE
                Executing Check 9 of 11: Klayout Metal Minimum Clear Area Density

        
    
        
            


            [11/21/22 13:57:50 PST] KLAYOUT METAL MINIMUM CLEAR AREA DENSITY CHECK PASSED
                The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

        
    
        
            


            [11/21/22 13:57:50 PST] STEP UPDATE
                Executing Check 10 of 11: Klayout Pin Label Purposes Overlapping Drawing

        
    
        
            


            [11/21/22 13:57:51 PST] EXCEPTION
                Script error code: 1

Thanks for looking into this!

Thank you, and apologies again for the inconvenience