Hi, I git cloned caravel GitHub in my directory. T...
# ieee-sscs-dc-22
s
Hi, I git cloned caravel GitHub in my directory. Then, I opened "user_analog_project_wrapper.mag" in Magic and placed my design in the Caravel Wrapper to manually connect to the pins, but I think two pins are missing in the left corner of the wrapper, gpio_analog[18] and gpio_analog[19]. I need a wrapper with mixed signal pads. The one that is based on the attached picture. Could anyone help me? Thanks
m
@sepide asgari Do you need bare pins with no esd protection or just analog pins? If you do not need bare pins, I think you can configure the gpios as analog ports on
user_project_wrapper
.
s
Thank you for your reply. Which one should we use for mixed-signal pads? When I use "user_project_wrapper", metal 4 and metal 5 are reserved for power routing. Since I have used these metals in my own design, it makes many wrong connections. So, I want to use an empty wrapper without any power routing in the middle to have the pin names in the first picture that I sent. Thanks
m
The default
user_project_wrapper
for
caravel
is just a place holder. Normally, you’d run openlane flow.tcl on
user_project_wrapper
and it will connect the macros and do all the wiring. You can however, do the top level wiring yourself. (I think).
s
If we place an analog design, which wrapper should we use? Should we use Openlane again for routing? Or can we do it manually? Thanks
m
The gpio cells have minimum width connections, but the bare analog pads have wider connections. If you need wider output paths,
user_analog_project_wrapper
would be better, I imagine. If it’s just analog signals and you don’t care about parasitics too much, you could probably use
user_project_wrapper
and have openlane route everything. You’d need to create a top level verilog rtl file for the connections.