Hi! I'm trying to port SonarOnChip to 180nm (I am working here) and I'm getting the following error during the floorplan OpenLane log:

[WARNING]: OpenLane may not function properly: Container manifest not found. What this likely means is that the container is severely out of date.
child process exited abnormally
[INFO]: Using configuration in 'OpenLane/designs/SonarOnChip/config.tcl'...
[INFO]: PDK Root: /content/pdks
[INFO]: Process Design Kit: gf180mcuC
[INFO]: Standard Cell Library: gf180mcu_fd_sc_mcu7t5v0
[INFO]: Optimization Standard Cell Library: gf180mcu_fd_sc_mcu7t5v0
[INFO]: Run Directory: /content/OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_02.23.19
[INFO]: Preparing LEF files for the nom corner...
[STEP 1]
[INFO]: Running Synthesis (log: OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_02.23.19/logs/synthesis/1-synthesis.log)...
[STEP 2]
[INFO]: Running Single-Corner Static Timing Analysis (log: OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_02.23.19/logs/synthesis/2-sta.log)...
[STEP 3]
[INFO]: Running Initial Floorplanning (log: OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_02.23.19/logs/floorplan/3-initial_fp.log)...
[ERROR]: Floorplanning failed
[ERROR]: module $_DLATCH_N_ not found in /content/OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_02.23.19/tmp/merged.nom.lef
[ERROR]: Check whether EXTRA_LEFS is set appropriately
[INFO]: Saving current set of views in 'OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_02.23.19/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_02.23.19/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_02.23.19/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.

(.../logs/floorplan/3-initial_fp.log):

OpenROAD dc11f5970c23ff81770fcbf705737516dad90b23  
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored. 
[INFO ODB-0222] Reading LEF file: /content/OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_01.49.39/tmp/merged.nom.lef 
[INFO ODB-0223]    Created 13 technology layers 
[INFO ODB-0224]    Created 60 technology vias 
[INFO ODB-0225]    Created 229 library cells 
[INFO ODB-0226] Finished LEF file: /content/OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_01.49.39/tmp/merged.nom.lef 
Reading netlist... 
[WARNING STA-0198] /content/OpenLane/designs/SonarOnChip/runs/RUN_2022.11.09_01.49.39/results/synthesis/SonarOnChip.v line 33077, module $_DLATCH_N_ not found. Creating black box for \filt.add1_reg[0] . 
[WARNING ORD-1013] instance filt.add1_reg\[0\] LEF master $_DLATCH_N_ not found. 
[WARNING ORD-1013] instance filt.add1_reg\[10\] LEF master $_DLATCH_N_ not found. 
[WARNING ORD-1013] instance filt.add1_reg\[11\] LEF master $_DLATCH_N_ not found. 
[WARNING ORD-1013] instance filt.add1_reg\[12\] LEF master $_DLATCH_N_ not found. 
[WARNING ORD-1013] instance filt.add1_reg\[13\] LEF master $_DLATCH_N_ not found. 
[WARNING ORD-1013] instance filt.add1_reg\[14\] LEF master $_DLATCH_N_ not found. 
[WARNING ORD-1013] instance filt.add1_reg\[15\] LEF master $_DLATCH_N_ not found.

Here is an extract from lines 33077 to 33095:

\$_DLATCH_N_ \filt.add1_reg[0] /* 9733 */ ( 
   .D(0770), 
   .E(0000), 
   .Q(\filt.add1[0] ) 
 ); 
 \$_DLATCH_N_ \filt.add1_reg[1] /* 9734 */ ( 
   .D(0777), 
   .E(0000), 
   .Q(\filt.add1[1] ) 
 ); 
 \$_DLATCH_N_ \filt.add1_reg[2] /* 9735 */ ( 
   .D(0778), 
   .E(0000), 
   .Q(\filt.add1[2] ) 
 ); 
 \$_DLATCH_N_ \filt.add1_reg[3] /* 9736 */ ( 
   .D(0779), 
   .E(0000), 
   .Q(\filt.add1[3] )

PDK and STD_CELL_LIBRARY that I'm using are:

%env PDK=gf180mcuC 
%env STD_CELL_LIBRARY=gf180mcu_fd_sc_mcu7t5v0 
%env STD_CELL_LIBRARY_OPT=gf180mcu_fd_sc_mcu7t5v0

What std should be $_DLATCH_N_? is "$_DLATCH_N_" expected in the synthesis results?

Standard cell reference missing for DLATCH in gf180 pdk. File issue here: https://github.com/google/gf180mcu-pdk/issues

There are two problems • You shouldn't instantiate _DLATCH_N_ directly - that is an primitive that yosys uses for an inferred latch. • The latch_map.v is missing which is an open_pdks issue

Hi Matt, I didn't instantiate _DLATCH_N_ directly; The lines that I shared are part of the synthesis results Regarding the question about latch based design, not really, that the design is latch based is not a requirement

@Mauricio Montanares also make sure to use the latest PDK from volare rather than the pre-released version that you currently fetch in the codelab.

%env PDK_FAMILY=gf180mcu
%env PDK=gf180mcuC
!cd OpenLane && make
%env PDK_ROOT=/content/OpenLane/pdks

@Mauricio Montanares: The amount of unhelpful or misleading information in this thread is kind of alarming. . . Anyway, the base problem is this: Yosys/ABC only deals with certain types of base mappings to standard cells, and that includes combination logic gates an various kinds of flip-flops. Beyond that, it's up to the PDK to provide mappings from standard cell library cells to the different kinds of "intermediate form" structures that Yosys defines. In some cases, like adders, yosys will provide some default mapping to regular standard cells, and if the standard cell library happens to have full- and half-adders, then you can define mappings that result in more efficient adders. However, a latch is a basic function and there is no way to define a reliably working latch out of combinational cells (maybe with the cross-coupled NAND gate structure, but I don't think any tool would dare to do that with potentially arbitrary timing between the components). The good news is that as long as there is a latch component in the standard cell library, it is relatively easy to define a verilog file that does that mapping for Yosys/ABC. And it can just be dropped into your project, and does not need to be integrated into Openlane/OpenROAD (although it's a lot more convenient when it is). The file that you want will look something like this (defines the mapping for a negative-enabled latch):

module \$_DLATCH_P_ (input E, input D, output Q);
  gf180mcu_fd_sc_mcu7t5v0__latq_1 _TECHMAP_DLATCH_P (
    //# {{data|Data Signals}}
    .D(D),
    .Q(Q),

    //# {{clocks|Clocking}}
    .GATE(E)
  );
endmodule

Note that the GF process has a positive-enabled latch but no negative-enabled latch. I believe that if you have at least one of them defined, then Yosys/ABC will rework the sense of the enable as needed to be compatible with the type that you have defined. Once you have your mapping file (call the file above, say,

yosys_mapping.v

), then you just need to put that file in the

openlane/<cellname>/

directory where you are running openlane, and then in that cell's

config.tcl

setup file for the synthesis run, add the following line:

set ::env(SYNTH_EXTRA_MAPPING_FILE) $script_dir/yosys_mapping.v

That will tell Openlane to add the mapping file when it runs the synthesis, and everything should work as you would expect.

Got it!! Thanks @Tim Edwards for the detailed explanation I will try what you mention and I will let you know in this thread the results

@Tim Edwards This should be part of the PDK setup and require no user intervention

@Matt Liberty: Yes, absolutely it should.