Hi @Tim Edwards, thank you for the help this morning answering my question about the pnp transistors. We were missing two layers needed for the connections (licon and mcon). We almost got our LVS clean, yet we have one remaining issue with these pnp devices. When we extract the layout, it shows two warnings (see screenshot) for one of these pnp's. We have the exact number of nets and devices, yet there is one extra pnp connected to the GND net (see comp.out file). Our schematic and layout is attached here also, along with their respective netlists. If you have some time to take a look at these, and give us some direction, it would be highly appreciated! @Justin Cash

setting

export NETGEN_COLUMNS=80

before running LVS will give you wider columns that might be easier to debug. Looks like connectivity to your pnp collector is not being extracted. magic doesn’t see it as a port so there are no connections to higher hierarchies. Check that the pdif in the center has licon, li, mcon, met1, and via.

@Mitch Bailey thank you for the suggestion. We will double check the pdif connection layers. Just for a sanity check, the collector is the outermost pdif, and emitter is the center pdif, right? So we should check both regions to make sure we are not missing anything.

@Andalib Nizam: It's very hard to see the layout connections from a screenshot. Please post the .mag file.

@Tim Edwards I believe the pnp transistor terminals in spice are extracted C B E, correct? I think the magic rule extracts the center pdif as the collector, the nwell as the base and the psubstrate (connected by surrounding ptap) as the emitter. Is that a correct interpretation?

@Mitch Bailey: The center pdiff is the emitter. The ring around the perimeter is the collector.

Thanks for the correction.

@Tim Edwards, here is the mag file:

@Andalib Nizam: Ah, please use the cell

sky130_fd_pr__rf_pnp_05v5_W0p68L0p68

(with the

_rf_

in the name). It is the exact same layout, and the same device model. The difference is that it has ports marked for the collector, emitter, and base, and is marked with a property that tells magic to extract it as the specific device model equal to the subcircuit name. Otherwise, it will not extract correctly and it will fail LVS (and maybe simulation).

@Tim Edwards, Thanks a lot! We are going to replace the BJTs now with this one and try.

@Andalib Nizam could you create a tarball of your mag and xschem directories and post that?

tar czf bgr.tgz mag xschem

There’s not enough information for me to check your results.

@Mitch Bailey, see the attachment please. Also, how to I see details on any Netgen warnings? I was looking for a log file or such but could not find one.

@Andalib Nizam: It appears that I did not put the RF versions of the bipolar transistors in the device list in the netgen setup file. They should be added along with the other bipolar devices, or else netgen won't recognize the PNP as a device (since it's defined as a subcircuit). I will update the PDK (in open_pdks) to correct this.

Your original comp.out file had

sky130_fd_pr__pnp_05v5_W0p68L0p68

in the layout and

sky130_fd_pr__pnp_05v5_W3p40L3p40

in the schematic. The these are considered separate device types and cause LVS mismatch.

@Mitch Bailey, Oops. Sorry about that. Here's the one with all the mag files.

@Tim Edwards It looks like the layout RF versions are just wrappers for the normal versions (maybe with pin added).

* NGSPICE file created from BGR1.ext - technology: sky130A

.subckt sky130_fd_pr__rf_pnp_05v5_W0p68L0p68 Base Collector Emitter m=1
X0 Collector Base Emitter sky130_fd_pr__pnp_05v5_W0p68L0p68
.ends
...
.subckt sky130_fd_pr__rf_pnp_05v5_W3p40L3p40 Emitter Collector Base m=1
X0 Collector Base Emitter sky130_fd_pr__pnp_05v5_W3p40L3p40
.ends

So you may not need to change the setup file. @Andalib Nizam Can you check that the pnp model names match between the layout and the schematic? If the schematic is correct, you might try changing the layout to

sky130_fd_pr__rf_pnp_05v5_W3p40L3p40

@Mitch Bailey, Sounds good. We will replace the 0.68x0.68 with 3.4x3.4 and see if it passes LVS. Thank you!

You have vertical

li

and

met1

overlapping, probably intended to reduce resistance, but the

met1

is not attached to ground.