@Mitch Bailey Hello I'm using SRAM macros in my design but they are not being connected to the power grid of my core. I'm using the following for macro connection:

set ::env(FP_PDN_MACRO_HOOKS) "soc_top.u_top.imem.iccm vccd1 vssd1 vccd1 vssd1, soc_top.u.dmem.dccm vccd1 vssd1 vccd1 vssd1"

can you share your repo? Need to confirm how module got instantiated

@Hamza Saeed Can you check your logs to see if there are any messages related to macro power connections? Maybe try `grep FP_PDN_MACRO_HOOKS `find . -name '*log*'`` or `grep soc_top.u_top..mem `find . -name '*log*'``

@Mitch Bailey Sorry for the late reply my laptop broke down. I checked my LVS report which says this: ---------------------- LVS reports: net count difference = 4 device count difference = 0 unmatched nets = 1153 unmatched devices = 176 unmatched pins = 0 property failures = 0 Total errors = 1333 ---------------------- Also, I checked lef.log file which shows this: Number of devices: 14565 |Number of devices: 14565 Number of nets: 14675 Mismatch |Number of nets: 14671 Mismatch

Just a guess, but I’m thinking that maybe the macro name in verilog doesn’t match the

macro.cfg

, and

config.tcl

files. I see no errors for

soc_top.u.dmem.dccm

but errors for

soc_top.u_top.imem.iccm

. Maybe it should be

soc_top.u.imem.iccm

? If so, you need to change your

macro.cfg

and

config.tcl

files.

@Hamza Saeed https://github.com/merledu/caravel_soc_now/blob/mpw-6/openlane/user_project_wrapper/config.tcl is not matching our thread for

FP_PDN_MACRO_HOOKS

. Share right repo or updated link

@Vijayan Krishnan Actually I'm using the RTL code only from this repo

Can you post

$::env(DESIGN_DIR)/macro_placement.cfg

too?

Here

Zip your design directory with source files and upload here

@Hamza Saeed Could it be that you’re missing a backslash?

Net: soc_top.u_top.imem.iccm_133/HI        |Net: \soc_top.u_top.dmem.sram_dout1[19]

@Mitch Bailey I'm using the correct macro name. Adding a backslash is giving this error:

AssertionError: ('Macros not found:', {'\\soc_top.u_top.dmem.dccm': ['630000', '50000', 'W'], '\\soc_top.u_top.imem.iccm': ['630000', '555000', 'W']})

backslashes may be tricky in tcl. You have the macro name for placement and then you have the pdn connection. I don’t know that the routines handle backslashes the same. You could try removing the backslashes from the verilog.

What is the goal of this project? Testing against OpenLane flow or MPW shuttle submission? The issue is with macro placement. why you've placed `W`side? any specific reasons? By placing

N

not facing any LVS issues. Another point use

GRT_OBS

for SRAM sizes to avoid DRC errors.

@Vijayan Krishnan Its for MPW shuttle. No specific reason. I was having routing congestion too many times with

N

side. So I tried with

W

but ended up with LVS. Why it was having connection issue with

W

side?

@Hamza Saeed In your macro.cfg file you specify the orientation as

W

soc_top.u_top.dmem.dccm 630 50 W
soc_top.u_top.imem.iccm 630 555 W

This does not mean the right side, but instead is converted to an orientation in

openlane/scripts/odbpy/manual_macro_place.py

LEF2OA_MAP = {
    "N": "R0",
    "S": "R180",
    "W": "R90",
    "E": "R270",
    "FN": "MY",
    "FS": "MX",
    "FW": "MXR90",
    "FE": "MYR90",
}

I assume the problem you have is when you place the macro rotated 90 degrees, the power straps don’t connect.

@Vijayan Krishnan I'm having these DRCs Am I using

GRT_OBS

correctly?

can you share

macro.cfg

?

macro_placement.cfg

Its known issue. As its showing DRC errors only to macro location, skip drc check using following configuration

set ::env(QUIT_ON_MAGIC_DRC) 0

@Vijayan Krishnan Hey, need some help here please. I'm having this LVS issue when I set

DESIGN_IS_CORE {0}

. When I set it to 1 the flow completes successfully.

LVS reports:
    net count difference = 4
    device count difference = 0
    unmatched nets = 1004
    unmatched devices = 185
    unmatched pins = 258
    property failures = 0

Total errors = 1451

_____

Net: soc_top.u_top.dmem.dccm_125/HI        |(no matching net)
  sky130_fd_sc_hd__conb_1/HI = 1           |
                                           |
Net: soc_top.u_top.imem.iccm_130/HI        |(no matching net)
  sky130_fd_sc_hd__conb_1/HI = 1           |
                                           |
Net: soc_top.u_top.dmem.dccm_119/HI        |(no matching net)
  sky130_fd_sc_hd__conb_1/HI = 1           |
                                           |
Net: soc_top.u_top.imem.iccm_135/HI        |(no matching net)
  sky130_fd_sc_hd__conb_1/HI = 1           |

Net: soc_top.u_top.dmem.dccm_125/HI        |(no matching net)                          
  sky130_fd_sc_hd__conb_1/HI = 1           |                                           
                                           |                                           
Net: soc_top.u_top.imem.iccm_130/HI        |(no matching net)                          
  sky130_fd_sc_hd__conb_1/HI = 1           |                                           
                                           |                                           
Net: soc_top.u_top.dmem.dccm_119/HI        |(no matching net)                          
  sky130_fd_sc_hd__conb_1/HI = 1           |                                           
                                           |                                           
Net: soc_top.u_top.imem.iccm_135/HI        |(no matching net)                          
  sky130_fd_sc_hd__conb_1/HI = 1           |                                           
---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------
(no matching net)                          |Net: vccd1                                 
                                           |  sky130_fd_sc_hd__buf_4/VPB = 168         
                                           |  sky130_fd_sc_hd__buf_4/VPWR = 168

Some of pins connected to tie high, those cells missing power supply.

vccd1

not connected properly

@Vijayan Krishnan what can be done to resolve this? I tried different configurations but couldn't resolve this issue.

@Mitch Bailey plz help on this

Can you examine the layout to verify that the

conb

cells are not in cell rows with

tapvpwrvgnd

cells.