Hi @Tim Edwards, I tried performing LVS extraction on the user_analog_project_wrapper. However, I get some warnings of shorted ports. This is expected, since I am configuring the io ports to be output/input. However, in my extracted spice netlist, I do not see vccd1 or vccd2 at all, and all power connections are connected to vssd2. I went back to Magic and checked the connectivity, and I can confirm that power and ground are not shorted. I was wondering if you could take a look. Thanks. The wrapper repo is https://github.com/r09g/iadc_caravel_wrapper

The "proper" way to handle this is not in the example (which is my fault); where you have shorted ports, the recommended procedure is to divide off the different net names using thin metal resistors in the layout (e.g., "rm3" in magic). There is another method that I recently debugged and got working, which is to use "ext2spice short resistor". That's basically an automated way to do the same thing. Magic will still produce those error messages, but you'll get an output netlist that represents all of the ports, and the LVS will handle it as well.

Got it, thanks!

Are you allowed to connect power pins to io? Isnt that going to be an ESD issue at fabrication? I thought tie cells were supposed to be used

@Tim Edwards I have another problem that I don't really understand. I added rmetal and performed LVS extraction. However, I see vccd2 and vssd1 having a rmetal5 in between, which is scary. However, I try to check connectivity in Magic with all cells expanded, and I don't see any shorts. Furthermore, I don't see vccd1 port in the extracted LVS netlist. vccd2 is supposed to connect to vccd1 through rmetal5.

@Arman Avetisyan: In principle, yes, it's better to tie digital signals off to a tie cell rather than shorting them to a power supply, or at least to short them to a power supply through a resistor (which is what the tie cells are). But only "antenna" type connections are an issue at fabrication. Hard-tying a gate to a power supply is an ESD issue during use, but a fairly minor ESD issue, and not a huge concern for a test chip.

My layout can be found under https://github.com/r09g/iadc_caravel_wrapper/tree/main/gds. Thanks

I don't see any power-ground shorts in the layout, but then I don't see any metal resistors, either.

Hmmm, I pushed a new update with rmetal 5 placed right next to the vccd2 and vssd2 pins.

@Raymond Yang: I used a "divide and conquer" strategy of slicing up the vccd1 power net into pieces, and I found that the cell instance

sky130_fd_sc_hd__clkbuf4_35

is wired up backwards to power and ground.

Wow. Fixing the problem right away and trying extraction again.