Hello I have a rather large digital design that get some XOR errors. I am flattening my design with the user_project_wrapper, so no separate hardening of my design. The XOR errors are on the ports and labels. Some pins look a bit malformed, like one below. Also there is an error in the areaId layer. Are these something to worry about? (The design is magic DRC clean with sky130A. I hit the error with holes in M1 when using sky130B). Thanks!

Are these caravel precheck errors?

No, these are from the openlane flow.

Are the XOR errors comparing klayout gds to magic gds?

Yes

Caravel precheck XOR check is probably checking something else. Openlane XOR compares magic and klayout gds. Caravel precheck XOR compares the outer ring of pins and other layers from `user_project_wrapper`/`user_analog_project_wrapper` that connect with `caravel`/`caravan`.

There was some period of time in which the standard cells for the B variant were missing the hole area specification for metal1 and metal2 in the technology LEF files, which caused the OpenROAD router not to consider such situations as errors. This should have been fixed a long time ago (open_pdks version 1.0.318, from July 24).