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Hello All,
We havte been running precheck on the online Efabless platform to the (almost) finished top layout of our project. We currently get a consistency error related to ports, please see the reports below. What is it exactly checking in this step?
<@U016EM8L91B> <@U017X0NM2E7>

its a simplified LVS. Has your design passed lvs?

Often what this means is that you connected several analog or power pins together;  the extraction produces only one name for the net, so one of the ports disappears from the netlist.  If that's the case, then the solution is to put a metal resistor near the ports to logically separate the port from the rest of the net, so all the port names will appear in the netlist.

Thanks a lot <@U016EM8L91B> 
CC <@U03B44EKP36>

hello <@U016EM8L91B>, just to understand clearly: your recommendation is to add at layout level (in magic) the metal resistors between the shorted ports, so they are extracted in the netgen-generated netlist, right?

Yes, that's right (requires adding the resistor to any schematic view you have of the same circuit, to pass LVS).