Hello everyone, I am performing prechecks of one of my analog design. I am getting this check failed shown in S.S below: I performed the prechecks locally and all the checks were passed. This is happening with 2 different projects. Can anyone guide me what is this error and How can it be mitigated?

@Mudassir Ali is your local precheck up-to-date? You’ll need to copy the

caravel/verilog/rtl/user_defines.v

file to your

verilog/rtl

directory and set the io types for each of your pins.

It worked thank you