Hi all We are facing an issue with yosys during synthesizing our design. The synthesizer is generating registers with unexpected names which create issues in post synthesis STA and cause syntax errors. This issue is only with first register generated at start of every module rest of registers are fine. This issue arises for "elobarate only" variable for synthesis as well as when synthesizing with the project wrapper.We have tried altering the scripts for yosys in openlane namely we have tried adding "opt_clean -purge" as well as removing "-noattrib" switch and adding "-renameprefix" with value <//> to "write_verilog" command in order to comment out the unwanted regs but to no affect. Kindly suggest a way to overcome this issue. Any help is much appriciated.

these are used to ensure correct simulation behaviour of 'always @*' blocks at startup in the output verilog - however, synthesised verilog output shouldn't have any of these

@gatecat we are not using any always block having @(*) inside there sensitivity list.

that doesn't matter - Yosys is using these in its output verilog representation of non-synthesised designs

I did not get, what you want to say ?

Have you tried to lint your Verilog code with iverilog and verilator? This usually gives good hints for unexpected coding errors which could cause issues during synthesis.