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Hi, I am running gate level simulation with sky130_fd_sc_hs, but i guess i lost this module "sky130_fd_sc_hs__u_vpwr_vgnd.v". Do you guys ever have a same issue? or any comments? thank you

<@U045K6Q2SJ2> I think this is an empty module. In `sky130_fd_sc_hd` there’s a similar cell
```module sky130_fd_sc_hd__tapvpwrvgnd (
    VPWR,
    VGND,
    VPB ,
    VNB
);

    // Module ports
    input VPWR;
    input VGND;
    input VPB ;
    input VNB ;
     // No contents.
endmodule```
Maybe you could copy this?

I guess this one is different. Because it is instantiate on every module of verilog file and also in out is different. This is the example:

```module sky130_fd_sc_hs__a2bb2o (
    VPWR,
    VGND,
    X   ,
    A1_N,
    A2_N,
    B1  ,
    B2
);

    // Module ports
    input  VPWR;
    input  VGND;
    output X   ;
    input  A1_N;
    input  A2_N;
    input  B1  ;
    input  B2  ;

    // Local signals
    wire	B2 and0_out          ;
    wire	B2 nor0_out          ;
    wire    or0_out_X         ;
    wire    u_vpwr_vgnd0_out_X;

    //                           Name          Output              Other arguments
    and                          and0         (and0_out          , B1, B2               );
    nor                          nor0         (nor0_out          , A1_N, A2_N           );
    or                           or0          (or0_out_X         , nor0_out, and0_out   );
    sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
    buf                          buf0         (X                 , u_vpwr_vgnd0_out_X   );

endmodule```

```sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);```
please take a look on that instantiate

<@U045K6Q2SJ2> I see what you mean.
<@U016EM8L91B> many if not all of the `hs` library verilog cells have the output buffered and have `sky130_fd_sc_hs__u_vpwr_vgnd` before the buffer. This module is not defined anywhere. Also, at least some of the layout cells that I looked at don’t actually have a buffer. See <https://diychip.org/sky130/sky130_fd_sc_hs/cells/a31o/>

I got it. So, to do the gate level simulation do i have to remove the buffer? comment uncomment

The netlists I see online include `sky130_fd_sc_hs__u_vpwr_vgnd` (See <https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs/blob/main/cells/buf/sky130_fd_sc_hs__buf.functional.v>)
```// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"```
However, this file doesn’t appear to exist. I’m not a verilog expert, but you might be able to use something like
```module sky130_fd_sc_hs__u_vpwr_vgnd (OUT, IN, VPWR, VGND);
  input IN;
  output OUT;
  inout VPWR;
  inout VGND;
  assign OUT = IN;
endmodule```