Hello all We managed to generate our project in the efabless open-source-silicon.dev #ieee-sscs-dc-22

Hello all, We managed to generate our project in t...

Jorge Marin

10/25/2022, 5:59 PM

Hello all, We managed to generate our project in the efabless platform: https://platform.efabless.com/projects/1427 Nevertheless, we are having trouble with our GDS size, since our power transistors are generated using TCL scripts in a flattened fashion. We need to compress the 250MB file to upload to Github, but then when we try to run the online precheck, it took long time and was aborted by the administrator. Can anyone here guide us with this issue?

Jorge Marin

10/26/2022, 2:57 PM

hello @jeffdi @Tim Edwards @Boris Murmann @Mitch Bailey, we need help with this to know whch actions we need to take to succesfully submit our design. We did a second precheck on the platform, you can see the report below. Two questions: 1. why does it complain about the gds.gz failing parsing in the "PARSING LAYOUT FAILED" step? 2. why do we see an exception at the end? "[10/25/22 140847 PDT] EXCEPTION Script error code: 1"

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[10/25/22 11:41:30 PDT] SUBMITTED






[10/25/22 14:00:39 PDT] STARTED






[10/25/22 14:00:41 PDT] PROJECT GIT INFO
Repository: <https://github.com/JorgeMarinN/3LFCC_AC3E_Tapeout.git> | Branch: sscspico | Commit: d1722431158136ae436d191a4287b9731e167898






[10/25/22 14:00:41 PDT] EXTRACTING FILES
Extracting compressed files in: sscs_pico_chip_6






[10/25/22 14:00:42 PDT] PROJECT TYPE INFO
analog






[10/25/22 14:00:43 PDT] PROJECT GDS INFO
user_analog_project_wrapper: 3bb2086d68aa6a78a3b9d37e884dea1396a87f20






[10/25/22 14:00:43 PDT] TOOLS INFO
KLayout: v0.27.10 | Magic: v8.3.315






[10/25/22 14:00:43 PDT] PDKS INFO
PDK: sky130B | Open PDKs: 05af1d05227419f0955cd98610351f4680575b95 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb






[10/25/22 14:00:43 PDT] START
Precheck Started, the full log 'precheck.log' will be located in 'sscs_pico_chip_6/jobs/mpw_precheck/09b26786-27f2-4766-892b-9334e3698b42/logs'






[10/25/22 14:00:43 PDT] PRECHECK SEQUENCE
Precheck will run the following checks: [Makefile, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]






[10/25/22 14:00:43 PDT] STEP UPDATE
Executing Check 1 of 11: Makefile






[10/25/22 14:00:43 PDT] MAKEFILE CHECK PASSED
Makefile valid.






[10/25/22 14:00:43 PDT] STEP UPDATE
Executing Check 2 of 11: Consistency






[10/25/22 14:00:46 PDT] PARSING LAYOUT FAILED
The user_analog_project_wrapper layout fails parsing because: Top module: user_analog_project_wrapper is not found in sscs_pico_chip_6/gds/user_analog_project_wrapper.gds.






[10/25/22 14:00:46 PDT] CONSISTENCY CHECK FAILED
The user netlist and the top netlist are not valid.






[10/25/22 14:00:46 PDT] STEP UPDATE
Executing Check 3 of 11: GPIO-Defines






[10/25/22 14:00:47 PDT] GPIO-DEFINES: ERROR IN VERILOG/RTL/USER_DEFINES.V
Directives(22) still placeholder (13'hXXXX) or not hex-literal: USER_CONFIG_GPIO_5_INIT=13'hXXXX USER_CONFIG_GPIO_6_INIT=13'hXXXX USER_CONFIG_GPIO_7_INIT=13'hXXXX USER_CONFIG_GPIO_8_INIT=13'hXXXX USER_CONFIG_GPIO_9_INIT=13'hXXXX USER_CONFIG_GPIO_10_INIT=13'hXXXX USER_CONFIG_GPIO_11_INIT=13'hXXXX USER_CONFIG_GPIO_12_INIT=13'hXXXX USER_CONFIG_GPIO_13_INIT=13'hXXXX USER_CONFIG_GPIO_14_INIT=13'hXXXX USER_CONFIG_GPIO_26_INIT=13'hXXXX USER_CONFIG_GPIO_27_INIT=13'hXXXX USER_CONFIG_GPIO_28_INIT=13'hXXXX USER_CONFIG_GPIO_29_INIT=13'hXXXX USER_CONFIG_GPIO_30_INIT=13'hXXXX USER_CONFIG_GPIO_31_INIT=13'hXXXX USER_CONFIG_GPIO_32_INIT=13'hXXXX USER_CONFIG_GPIO_33_INIT=13'hXXXX USER_CONFIG_GPIO_34_INIT=13'hXXXX USER_CONFIG_GPIO_35_INIT=13'hXXXX USER_CONFIG_GPIO_36_INIT=13'hXXXX USER_CONFIG_GPIO_37_INIT=13'hXXXX.. No report generated.






[10/25/22 14:00:47 PDT] GPIO-DEFINES CHECK FAILED
The user verilog/rtl/user_defines.v is not valid.






[10/25/22 14:00:47 PDT] STEP UPDATE
Executing Check 4 of 11: XOR






[10/25/22 14:00:49 PDT] XOR CHECK FAILED
The GDS file has non-conforming geometries.






[10/25/22 14:00:49 PDT] STEP UPDATE
Executing Check 5 of 11: Magic DRC






[10/25/22 14:01:02 PDT] MAGIC DRC CHECK PASSED
The GDS file, user_analog_project_wrapper.gds, has no DRC violations.






[10/25/22 14:01:02 PDT] STEP UPDATE
Executing Check 6 of 11: Klayout FEOL






[10/25/22 14:02:11 PDT] KLAYOUT FEOL CHECK FAILED
The GDS file, user_analog_project_wrapper.gds, has DRC violations.






[10/25/22 14:02:11 PDT] STEP UPDATE
Executing Check 7 of 11: Klayout BEOL






[10/25/22 14:07:59 PDT] KLAYOUT BEOL CHECK PASSED
The GDS file, user_analog_project_wrapper.gds, has no DRC violations.






[10/25/22 14:07:59 PDT] STEP UPDATE
Executing Check 8 of 11: Klayout Offgrid






[10/25/22 14:08:38 PDT] KLAYOUT OFFGRID CHECK PASSED
The GDS file, user_analog_project_wrapper.gds, has no DRC violations.






[10/25/22 14:08:38 PDT] STEP UPDATE
Executing Check 9 of 11: Klayout Metal Minimum Clear Area Density






[10/25/22 14:08:45 PDT] KLAYOUT METAL MINIMUM CLEAR AREA DENSITY CHECK PASSED
The GDS file, user_analog_project_wrapper.gds, has no DRC violations.






[10/25/22 14:08:45 PDT] STEP UPDATE
Executing Check 10 of 11: Klayout Pin Label Purposes Overlapping Drawing






[10/25/22 14:08:47 PDT] EXCEPTION
Script error code: 1

Mitch Bailey

10/26/2022, 3:41 PM

user_analog_project_wrapper

in your gds file? You need to set up

verilog/rtl/user_defines.v

with the default I/O pad settings.

Tim Edwards

10/26/2022, 4:24 PM

You have multiple errors and will need to address each one in turn. Most of the error reports are pretty clear, e.g., the first one is:

Copy code

The user_analog_project_wrapper layout fails parsing because: Top module: user_analog_project_wrapper is not found in sscs_pico_chip_6/gds/user_analog_project_wrapper.gds.

So you need to have your layout top level named

user_analog_project_wrapper

or else the system will not accept it. You have not edited the

user_defines.v

file (which was a requirement recently announced). You have "non-conforming geometries" in the layout, which generally means shapes (other than labels) with zero area. You have FEOL (i.e., below metal, meaning well/diffusion/implants/poly) DRC errors in the layout.

Jorge Marin

10/26/2022, 4:46 PM

Thanks a lot for the reply, we'll work on the errors Why doesn't it finish the checks and ends with an exception?

Tim Edwards

10/26/2022, 4:48 PM

That, I'm not sure, but possibly the zero-area geometry is causing problems with klayout.

Jorge Marin

10/26/2022, 4:53 PM

Thanks @Tim Edwards I'll take the opportunity to ask you: why Is this tapeout using sky130B? At the Chipathon we were told it would use the 130A version

Boris Murmann

10/26/2022, 4:58 PM

@Tim Edwards regarding A vs. B, this was also my understanding: https://open-source-silicon.slack.com/archives/C031R263TC7/p1659562295712639?thread_ts=1659540758.506449&cid=C031R263TC7

Tim Edwards

10/26/2022, 7:16 PM

I have logged an issue internally to the effect that we need to have information on which variant is being used for which tapeout in the information about upcoming shuttle runs on the Efabless website. Meanwhile, though, apparently there was a policy change that we would start supporting ReRAM on ChipIgnite runs, and I protested that we couldn't just do that without informing all of the users well in advance. Our current planning has ChipIgnite remaining on Sky130A until at least the end of November. Which ChipIgnite run is in question here?

Jorge Marin

10/26/2022, 7:17 PM

It's 2211Q run

Boris Murmann

10/26/2022, 7:17 PM

2211Q

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