Hi, I am doing post layout simulations of a simple inverter but the post layout output results is just a 1.8 v straight line. steps i have followed are: 1. created spice file from layout 2. inserted the path of layout spice file as ".include /home/mudassir/Desktop/magic_inv3_test/inverter.spice" in code_shown block 3. changed the type in symbol from subcircuit to primative. The screenshots of post and pre layout results are attached along with both the spice files. Am I doing any mistake??

the spice pin order does not match primitive pin order

No supply

post the tb netlist and schematic

netlist and screenshot of TB

inverter layout has no instance of inverter and neither the testbench netlist

The inverter instance is declared here

do you see a single line in a picture that is not in .subckt/ends? I dont. Therefore there are declaration of subckt but no instances

I think @Arman Avetisyan is right. Your

Inverter_tb.spice

has

x1 net1 vin vout GND inverter

but the screenshot of the included file has

.subckt inverter OUT VDD VSS IN

So

OUT=net1 VDD=vin VSS=vout IN=GND

which is probably not what you want.

oh nvm, i missed the first line

Right, thank you got it