Hi everyone, in precheck XOR check failed. Nearly all io pins are mismatching and I realized there are power pins at layer met2 and met3 located like an io pin. They are connected to no load but they are there though. Also when running user_project_wrapper, I need to define USE_POWER_PINS to make my modules synthesize, otherwise yosys returns an error and says there is no pin named vssd1. In my previous projects I never needed it. So I think in power pins are wrongly defined somewhere and makes wrapper consider power pins as io pins, but I couldn't find it.. In my github repository you can find all reproducibles and gds files inside. @jeffdi @Tim Edwards