(my best guess is I need to somehow increase li1_ca_density, but I don't know what that is and how to affect it)

Try to reduce your Macro DIE area .. Look like your macro design is small and you have given more die area and due this more TAP/De-Cap are added.

Thanks. For my understanding: empty space leads to more tap/decap leads to a low li1_ca_density? (what is li1_ca_density?)

You can refer this mail thread : It's the complement of the local interconnect layer that needs to have at least 0.4 density, i.e.

li1_ca_density = 1 - li1_density

. In other words you cannot exceed 60% material in the local interconnect layer. There were two way to fix the issue, 1) reduce the Macro area 2) Reduce the De-cap in the Macro Area https://skywater-pdk.slack.com/archives/C02KCG2DZK7/p1636901382096400

Thanks, I'll have a look at that. I've decreased the macro area of the individual hard macros, but I can't get them any smaller. It helped a bit, but didn't get me to 0.4. I'll try reducing the decap tomorrow. For reference, this is my current floorplan:

There is simple way of replacing foundry decap cells with decap cells from efabless. I did this using KLayout

@Dinesh A thanks so much for the suggestion, with the new decap_12 cell I'm at density 0.43!