Hi @Tim Edwards @Mitch Bailey I am failing the consistency check: Layout check where the user project gds doesn't match the structural netlist (missing module is puf_top.v). I edited the verilog/rtl/user_analog_project_wrapper.v to include the puf_top.v module which is defined in design.lvs.v which has the flat structural netlist after synthesis. I am not sure exactly what this check is doing, for example, is it checking lvs against this user_analog_project_wrapper.v netlist? Thank you so much for your help. Here is my repo: https://github.com/lsammarone/OpenPUF

This isn't a magic question. Can you move it to #shuttle-precheck?