Has anyone tried using the keep synthesis attribute? Is following the correct way to apply it to a signal named e1: (* keep *) wire[14:0] e1; ? If the attribute is successfully getting applied by yosys, does the synthesis log reflect it anywhere?

I tried. Yes it works. No log written regarding this. However, if you want to (keep) something it's likely that you are on the wrong track to fixing your original issue.

Thanks for answering @Arman Avetisyan. Well, I am designing a security chip where I do not want the tool to perform any kind of optimizations/retiming on certain modules/cells. Thus, adding this flag is more like precaution rather than a need. How did you verify that it is taking effect? If possible, can you please share some more details about your experiment, like what exact logic did you keep, and how did you verify it?

"Well, I am designing a security chip where I do not want the tool to perform any kind of optimizations/retiming on certain modules/cells." Keep does not achieve this. Maybe you want set_false_path which disables the timing checks. Still not sure why would you need anything like that. "Thus, adding this flag is more like precaution rather than a need." Avoid doing so. If you have logic issue, it will optimize away the logic => you will see before running the simulation that something is fishy => you will catch the root cause. "How did you verify that it is taking effect? If possible, can you please share some more details about your experiment, like what exact logic did you keep, and how did you verify it?" I had inverter-nand/nor chain in the NCO (numerically controlled oscillator) and since there was no input, just outputs, the yosys obviously optimized my logic away. Same happened in Vivado/Quartus. I added keep attribute to the nets+ports with inverter/nand/nors to make sure they are not optimized away. I saw in the schematic view and in the generated netlist the (previously optimized away) logic magically appeared.

Thanks a lot for the elaborate reply!