hi, I have an openram module inside my design, I excluded the verilog file from config.tcl and add macro parameters with: ### Macro PDN Connections set ::env(FP_PDN_MACRO_HOOKS) "\ sky130_sram_2kbyte_1rw1r_32x512_8 vccd1 vssd1" ### Macro Placement set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ $script_dir/../../verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v" set ::env(EXTRA_LEFS) "\ $script_dir/../../lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef" set ::env(EXTRA_GDS_FILES) "\ $script_dir/../../gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds" after the design timing and area report openlane gave error by complaining: [INFO]: Performing Manual Macro Placement... OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. [INFO ODB-0222] Reading LEF file: /home/mbaykenar/Desktop/first_asic/openlane/pulpino_top_wrapper/runs/pulpino_top_wrapper/tmp/merged.lef [INFO ODB-0223] Created 13 technology layers [INFO ODB-0224] Created 25 technology vias [INFO ODB-0225] Created 442 library cells [INFO ODB-0226] Finished LEF file: /home/mbaykenar/Desktop/first_asic/openlane/pulpino_top_wrapper/runs/pulpino_top_wrapper/tmp/merged.lef [INFO ODB-0127] Reading DEF file: /home/mbaykenar/Desktop/first_asic/openlane/pulpino_top_wrapper/runs/pulpino_top_wrapper/tmp/floorplan/4-io.def [INFO ODB-0128] Design: pulpino_top_wrapper [INFO ODB-0130] Created 609 pins. [INFO ODB-0131] Created 49901 components and 372609 component-terminals. [INFO ODB-0133] Created 50332 nets and 172761 connections. [INFO ODB-0134] Finished DEF file: /home/mbaykenar/Desktop/first_asic/openlane/pulpino_top_wrapper/runs/pulpino_top_wrapper/tmp/floorplan/4-io.def Placing the following macros: {'sky130_sram_2kbyte_1rw1r_32x512_8': ['590000', '370000', 'N']} Design name: pulpino_top_wrapper Traceback (most recent call last): File "/openlane/scripts/manual_macro_place.py", line 139, in <module> assert not macros, ("Macros not found:", macros) AssertionError: ('Macros not found:', {'sky130_sram_2kbyte_1rw1r_32x512_8': ['590000', '370000', 'N']}) [ERROR]: during executing: "openroad -python /openlane/scripts/manual_macro_place.py -l /home/mbaykenar/Desktop/first_asic/openlane/pulpino_top_wrapper/runs/pulpino_top_wrapper/tmp/merged.lef -id /home/mbaykenar/Desktop/first_asic/openlane/pulpino_top_wrapper/runs/pulpino_top_wrapper/tmp/floorplan/4-io.def -o /home/mbaykenar/Desktop/first_asic/openlane/pulpino_top_wrapper/runs/pulpino_top_wrapper/tmp/floorplan/4-io.macro_placement.def -c /home/mbaykenar/Desktop/first_asic/openlane/pulpino_top_wrapper/runs/pulpino_top_wrapper/tmp/placement/macro_placement.cfg -f |& tee >&@stdout /home/mbaykenar/Desktop/first_asic/openlane/pulpino_top_wrapper/runs/pulpino_top_wrapper/logs/placement/5-macro_placement.log" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: What could be reason for not finding openram macro ? Regards,

What are contents of

$script_dir/macro.cfg

? You probably want the instance name from your verilog file instead of the module name here.

set ::env(FP_PDN_MACRO_HOOKS) "\
   sky130_sram_2kbyte_1rw1r_32x512_8 vccd1 vssd1"

Thanks, You are right, but then I changed it and still got the same error now macro.cfg is: "open_ram_2k 590 370 N" and in config.tcl set ::env(FP_PDN_MACRO_HOOKS) "\ open_ram_2k vccd1 vssd1" and module instantiation is: sky130_sram_2kbyte_1rw1r_32x512_8 open_ram_2k( .clk0(clk), .csb0(1'b0), .web0(~(we_i & ~bypass_en_i)), .wmask0(be_i), .addr0(addr_i[10:2]), .din0(wdata_i), .dout0(ram_out_int), .clk1(1'b0), .csb1(1'b1), .addr1(9'b000000000), .dout1() );

Your module doesn't have any power connections.

it was due to sv2v (systemverilog to verilog) conversion now I added powers thanks but does this cause macros not found error ?

Looking at the code, I don't think missing power connections will cause macro not found error. Is

open_ram_2k

at the top level of your verilog?

no it is not, it is at the lower levels of hierarchy, may it be the reason? does a macro must be in the top level?

That might be the quickest solution.

hmmm, worth try it, last hours on mpw6, i have no other chance 🙂

For example, https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-five/slot-008

👍 thanks a lot