I have tried the same design on Synopsys Design Compiler and worked very well, but in Yosys it deletes all modules and keeps only the top while flattening the design. could anyone please help?

if yosys is removing the contents, it's because it has detected that the module does nothing. Maybe you didn't connect the outputs up to the top level?

modules instantiation on top is correct and there are wires on the top to connect everything to each other, and the strange thing is that the same design is working well on DC, so if there is something I miss on config or any other reason?

are you hardening the module?

sorry for being late https://github.com/MohamedAliYounis/ASU_GP22

I couldn't see anything obvious sorry

@Vijayan Krishnan could you take a look, please? 😅 this is the same problem I sked before in this thread: https://skywater-pdk.slack.com/archives/C016G7Z8GDR/p1654635956296399

core.v is your top design. do you checked your synthesized file, contains all instance as per core.v?

it contains only the top module instance

1. Its deleting the modules that are now flattened away. Nothing wrong with this 2. Without stats from DC its not clear what do you mean when you say DC is okay. 3. Without final cell stats and no stats from DC its practically impossible to make a conclusion.

@Arman Avetisyan • It deletes all the design.. I compared the number of cells with a small module of the design get hardened separately. And it's not correct at all. • And I synthesis the same design on Synopsys Design Compiler with no problems at all, so I'm confused about the reason that yosys did that.

I tried to checkout your repo but couldn't get past 'make setup'. If you can package a set of steps I can take a look