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I'm having issues when running make user_project_w...
# caravel
t
I'm having issues when running make user_project_wrapper. All power pins used are mismatched as shown in the log below: 
(no matching pin)                          |vccd1
(no matching pin)                          |vccd2
(no matching pin)                          |vdda1
(no matching pin)                          |vssa1
(no matching pin)                          |vssd1
(no matching pin)                          |vssd2
vccd1                                      |(no matching pin)
vccd2                                      |(no matching pin)
vdda1                                      |(no matching pin)
vssa1                                      |(no matching pin)
vssd1                                      |(no matching pin)
vssd2                                      |(no matching pin)
The error in the console is: 
Circuit bqmain contains no devices.
Circuit sar_10b contains no devices.
Contents of circuit 1:  Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 2 device instances.
Class: bqmain                instances:   1
Class: sar_10b               instances:   1
Circuit contains 204 nets, and 514 disconnected pins.
Contents of circuit 2:  Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 2 device instances.
Class: bqmain                instances:   1
Class: sar_10b               instances:   1
Circuit contains 204 nets, and 508 disconnected pins.
Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
Circuit 1 contains 204 nets,    Circuit 2 contains 204 nets.
Netlists match uniquely.
Result: Cells failed matching, or top level cell failed pin matching.
Logging to file "/home/openpdk/caravel/fct-iot-node-project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/30-user_project_wrapper.lef.log" disabled
LVS Done.
LVS reports:
net count difference = 0
device count difference = 0
unmatched nets = 0
unmatched devices = 0
unmatched pins = 6
property failures = 0
Total errors = 6
[ERROR]: There are LVS errors in the design according to Netgen LVS.
What could be the cause of this?
j
I had similar issues when I didn't specify that my macros should be connected to the power in the user_project_wrapper config.tcl. This could possibly be the issue.
t
I have it specified as follows:
j
Do you also have these power pins in user_project_wrapper.v ?
t
image.png,image.png
j
ah. Then I don't know whats the issue.
t
Ok, thank you for you help anyway 🙂
m
can you post a pic of your pdn or floorplan?
if the design is very small then it might not pick up the power lines
should be at least 220um tall to guarantee it gets + and - from 1st digital psu
t
The logs? Or are you referring to the positions of the macros?
m
pics are easy to understand
t
The smallest macro is roughly 528x163
m

https://skywater-pdk.slack.com/files/U0172QZ342D/F03KBUL2LRE/image.png▾

t
image.png
m
zoom on the small one pls?
t
image.png
m
Im sure that's it
it's not quite tall enough to guarantee it will get both + and -
you may get a fix by moving it slightly vertically
but probably easier is just reharden at least 220 um tall
t
I see, I'll try just that
Thank you
@Matt Venn I tried to fix it by moving but it doesn't seem to work. I don't know how to make it taller other than to rotate it 90º, since this is someone else's analog design.
@Christoph Weiser Sorry to bother you again, but do you happen to know how to connect your design to power through the caravel user_project_wrapper? In your "design.gds" it looks like it was done by hand.
c
@Tiago Silva: You're right I connected it by hand. But of course i also used the analog project wrapper, where it's pretty straightforward to do so. So I have really no idea how to do it in the normal wrapper.
m
you oculd try rotating it Tiago
t
I tried, but even then it still fails
m
Looks like you're trying to connect 2 power and 2 ground to 
sbar_10b0
with 
FP_PDN_MACRO_HOOKS
. I don't think that syntax is correct and the errors are silently ignored. Check your layout to verify.
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