hi all, during synthesis of my design (slightly modified version of ETH Zurich's famous PULPINO SoC), i got an error but there is no detailed info. I am adding "1-synthesis.log" file and my github repo: https://github.com/mbaykenar/first_asic Any help is appreciated !

child killed probably an out of memory kill

thanks, any suggestion? RAM is 16GB, maybe I can close browser, vscode etc all ?

https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1650317104192279?thread_ts=1650215768.620859&cid=C016H8WJMBR check this for increasing swap memory

I have 2, 2KB OpenRAM in my design. I was first trying to synth without OpenRAM macros to test first, which can cause as you said RAM exhaustion. I will now try with OpenRAM macros, maybe it can help

yes try to use pre-compiled RAM from PDK

i will try and tell the situaiton thanks

set ::env(DIE_AREA) "0 0 900 600"
set ::env(FP_SIZING) absolute
set ::env(PL_BASIC_PLACEMENT) 1

Comment above settings in your

config.tcl

increasing swap from 3 GB to 11 GB solved the problem, thanks a lot