Hi everyone, I am currently working with openRAM 1k 1rw1r SRAMs. We are getting quite a few DRV issues related to max transition. I am a little concerned the liberty file value for max_tran is unrealistic. This is the liberty file I am currently using: https://github.com/efabless/sky130_sram_macros/blob/main/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib However this max_tran portion is causing several DRV errors.

bus(addr0){
        bus_type  : addr; 
        direction  : input; 
        capacitance : 0.006889999999999999;  
        max_transition       : 0.04;
        pin(addr0[7:0]){

One thing I noticed is that another openRAM sky130 Macro repo, has a different liberty value that has 10x the size: https://github.com/ShonTaware/SRAM_SKY130/blob/main/OpenRAM/results/SRAM_32x1024/sram_32_1024_sky130A_FF_1p8V_25C.lib Specifically:

bus(addr0){
        bus_type  : addr; 
        direction  : input; 
        capacitance : 0.0098242;  
        max_transition       : 0.4;
        pin(addr0[9:0]){
        timing(){ 
            timing_type : setup_rising; 
            related_pin  : "clk0"; 
            rise_constraint(CONSTRAINT_TABLE) {
            values("0.009, 0.009, 0.009",\
                   "0.009, 0.009, 0.009",\
                   "0.009, 0.009, 0.009");
            }

Running with a manual change of these in our local liberty file removes all our DRV issues. Any and all thoughts on this are greatly appreciated. Also I am first time designer so let me know if there is anything above I need to clarify 🙂