Hi @Tim Edwards When I run netgen lvs on the gds extracted netlist, I run into an issue with the buses on my macros (32-bit buses), they have a '\' in front of the port. I flatten the bus in signoff so the verilog netlist matches the ports in the spice netlist for the macros. I tried to remove these '\', so they match the extracted netlist pins, but lvs does not pass. The report says netgen is recognizing some weird classes like c, [ and ( as seen in the netgen lvs report below. Do you know how to fix this? Thank you so much.

Could you post your gate level verilog and extracted spice netlist?