@Tim Edwards In the document(https://sky130-fd-pr-reram.readthedocs.io/en/latest/user_guide.html), it seems we don't need to worry about the top and bottom vias for designing, they are all defined by 'r1c' layer, but in my environment, I have a layer only appears at the RRAM device shown in the attached figure, but I can't see the name. The layout of a single RRAM and the layer list is shown below:

I'm not sure what you're concerned about. As the documentation says, there is only one "via" mask layer, and that gets divided up by the foundry, presumably by using the same mask to do the bottom half of the via, then processing the ReRAM layers, then using the same mask again to do the top half of the vias. You can't get it backwards.

Ok, thanks @Tim Edwards I thought there was some polarity but it doesn't sound like there is.