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Hi <@U016EM8L91B>, I have a modulator layout in ma...
# magic
r
Hi @Tim Edwards, I have a modulator layout in magic with two OTAs as instances placed in the layout. When I perform LVS extraction, I see that the VSS node for the OTA is not in the list of pins in the SPICE .subckt definition. However, when I open up the OTA layout and extract just the OTA, the pin list of the extracted SPICE netlist is correct (with VSS as a pin). Do you know what the problem might be? Thank you. (@Can Wang is trying to figure out this problem with me)
r
Need to recreate the the labels in the TOP may be ?
r
I connected all VSS of the instances using metal layers and created a VSS label at the top-level, also made that into a port
m
Check your extraction output to see if there is a short warning.
t
I can't tell without looking at the layout, but it's possible that VSS was not marked as a pin, and is being included in the pin list because it is the only substrate connection found, and that it is getting optimized out of the layout when extracted from the top level. But that's just a guess.
r
Here is the layout with LVS extraction warnings. I don't see any short warnings. I also highlighted the VSS connectivity at the top level with the OTA (circled in red)
t
Well, I meant the actual layout, not a screenshot of the layout in the ancient X11 graphics mode.
r
Oh, sorry about that, would you prefer the .mag files? or perhaps a link to the github repo would be more convenient?
t
A link to the github repo is easy and avoids posting lots of files to the slack channel.
r
Here's the link: https://github.com/r09g/incremental_delta_sigma_adc The layout should be under "design/analog_modulator/layout/analog_top/analog_top.mag" Thanks!
t
@Raymond Yang: Looking at your OTA layout, I see that it does not have any ports declared; the nets are labeled, but the labels are not ports. Because of that, magic will not assume any ports and will declare ports as it sees them connected from above in the hierarchy. That is not an error, but it does mean that if magic decides that a net like VSS is merged with something else, then the pin can get optimized out and disappear from the port list of the subcircuit. Otherwise, I do not see anything obviously wrong with the layout. Where is the schematic netlist that you are comparing against?
r
Perhaps I should make the ports first, save the .mag file, then place instance at a higher hierarchy? The schematic is under "design/analog_modulator/schematic/analog_top.sch". Appreciate your feedback and help!
t
Well, I don't really see anything that must be done to the layout. My recommendation would make it a bit easier to debug the LVS output. But I would like to run LVS myself to see what output it is generating, if you can tell me where the schematic netlist is, or how you invoke LVS.
r
I have all the netlists required under "design/analog_modulator/netlist/analog_top/", the analog_top.spice is the netlist generated with Xschem (gold netlist), the analog_top_layout_lvs.spice is the netlist extracted from Magic. To run LVS, I would run 
sh run_magic_extraction.sh
to extract the LVS netlist, then 
sh run_netgen_lvs.sh
to run LVS.
t
I'm not sure why I see labels marked as ports in your screenshot above, but in the layout that I cloned from the repository, they're just plain labels.
These two electrical short warnings are generated by extraction:
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Warning:  Ports "a_probe_3" and "out" are electrically shorted.
Warning:  Ports "a_probe_2" and "out" are electrically shorted.
They should have no bearing on the issue with 
VSS
, but just be aware that they can cause issues with LVS.
r
This is interesting, with what command could I view extraction warnings? Previously I used "feedback why" in Magic, but I might have missed electrical short warnings.
Did the extracted netlist on your end have VSS ports for 
ota
and 
ota_w_test
instances?
t
@Raymond Yang: I don't know what output logging the script generates. I just do extraction with 
extract do local ; extract all
and errors will be output to the console. So I ran LVS myself, and I do get errors at the level of 
ota_w_test
, but I don't see anything specifically related to VSS, which shows up in both netlists. What I do get is this:
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Class ota_w_test (0):  Merged 748 parallel devices.
Subcircuit summary:
Circuit 1: ota_w_test                      |Circuit 2: ota_w_test
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_lvt (80->9)        |sky130_fd_pr__pfet_01v8_lvt (72->8) **Mism
sky130_fd_pr__nfet_01v8_lvt (88->7)        |sky130_fd_pr__nfet_01v8_lvt (88->7)
sky130_fd_pr__nfet_01v8 (571->49)          |sky130_fd_pr__nfet_01v8 (548->48) **Mismat
sky130_fd_pr__pfet_01v8 (92->18)           |sky130_fd_pr__pfet_01v8 (86->17) **Mismatc
sc_cmfb (1)                                |sc_cmfb (1)
Number of devices: 84 **Mismatch**         |Number of devices: 81 **Mismatch**
Number of nets: 42                         |Number of nets: 42
---------------------------------------------------------------------------------------
which suggests an underlying problem with device counts (9 vs. 8, 48 vs. 48, 18 vs. 17).
r
Sorry, I made a mistake in my schematic, just pushed the correct schematic to the repo. The device counts should be correct. I have also attached my LVS report.
comp.out
t
@Raymond Yang: I pulled your corrections, and the 
ota_w_test
now passes. What I see is this:
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Subcircuit summary:
Circuit 1: clock_v2                        |Circuit 2: clock_v2
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__clkbuf_16 (16)            |sky130_fd_sc_hd__clkbuf_16 (16)
sky130_fd_pr__pfet_01v8_hvt (464->1)       |(no matching element)
sky130_fd_pr__nfet_01v8 (464->1)           |(no matching element)
sky130_fd_sc_hd__clkdlybuf4s50_1 (120)     |sky130_fd_sc_hd__clkdlybuf4s50_1 (120)
sky130_fd_sc_hd__clkinv_4 (12)             |sky130_fd_sc_hd__clkinv_4 (12)
sky130_fd_sc_hd__nand2_4 (4)               |sky130_fd_sc_hd__nand2_4 (4)
sky130_fd_sc_hd__dfxbp_1 (2)               |sky130_fd_sc_hd__dfxbp_1 (2)
sky130_fd_sc_hd__nand2_1 (5)               |sky130_fd_sc_hd__nand2_1 (5)
sky130_fd_sc_hd__clkinv_1 (7)              |sky130_fd_sc_hd__clkinv_1 (7)
sky130_fd_sc_hd__mux2_1 (1)                |sky130_fd_sc_hd__mux2_1 (1)
Number of devices: 169 **Mismatch**        |Number of devices: 167 **Mismatch**
Number of nets: 172                        |Number of nets: 172
---------------------------------------------------------------------------------------
which is due to the schematic side not representing the decap cells in the digital. It should be correctable simply by instantiating one each of the decap cells used in the layout in the schematic, and setting M to the number of that type of decap cell used.
r
I see, I will fix this. Thank you very much for your help!
I get different extraction and LVS results when I perform extraction on my end. For the same setup, my clock_v2 summary is:
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Subcircuit summary:
Circuit 1: clock_v2                        |Circuit 2: clock_v2                        
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__decap_4 (1)               |sky130_fd_sc_hd__decap_4 (1)               
sky130_fd_sc_hd__decap_3 (1)               |sky130_fd_sc_hd__decap_3 (1)               
sky130_fd_sc_hd__decap_8 (1)               |sky130_fd_sc_hd__decap_8 (1)               
sky130_fd_sc_hd__decap_12 (1)              |sky130_fd_sc_hd__decap_12 (1)              
sky130_fd_sc_hd__nand2_1 (5)               |sky130_fd_sc_hd__nand2_1 (5)               
sky130_fd_sc_hd__clkinv_4 (12)             |sky130_fd_sc_hd__clkinv_4 (12)             
sky130_fd_sc_hd__clkinv_1 (7)              |sky130_fd_sc_hd__clkinv_1 (7)              
sky130_fd_sc_hd__clkdlybuf4s50_1 (120)     |sky130_fd_sc_hd__clkdlybuf4s50_1 (120)     
sky130_fd_sc_hd__nand2_4 (4)               |sky130_fd_sc_hd__nand2_4 (4)               
sky130_fd_sc_hd__dfxbp_1 (2)               |sky130_fd_sc_hd__dfxbp_1 (2)               
sky130_fd_sc_hd__mux2_1 (1)                |sky130_fd_sc_hd__mux2_1 (1)                
sky130_fd_sc_hd__clkbuf_16 (16)            |sky130_fd_sc_hd__clkbuf_16 (16)            
Number of devices: 171                     |Number of devices: 171                     
Number of nets: 172 **Mismatch**           |Number of nets: 173 **Mismatch**           
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: clock_v2                        |Circuit 2: clock_v2                        

---------------------------------------------------------------------------------------
Net: VDD                                   |Net: VDD                                   
  sky130_fd_sc_hd__decap_4/VPB = 1         |  sky130_fd_sc_hd__decap_4/VPB = 1         
  sky130_fd_sc_hd__decap_4/VPWR = 1        |  sky130_fd_sc_hd__decap_4/VPWR = 1        
  sky130_fd_sc_hd__decap_3/VPB = 1         |  sky130_fd_sc_hd__decap_3/VPB = 1         
  sky130_fd_sc_hd__decap_3/VPWR = 1        |  sky130_fd_sc_hd__decap_3/VPWR = 1        
  sky130_fd_sc_hd__decap_8/VPB = 1         |  sky130_fd_sc_hd__decap_8/VPB = 1         
  sky130_fd_sc_hd__decap_8/VPWR = 1        |  sky130_fd_sc_hd__decap_8/VPWR = 1        
  sky130_fd_sc_hd__decap_12/VNB = 1        |  sky130_fd_sc_hd__decap_12/VPB = 1        
  sky130_fd_sc_hd__nand2_1/VPB = 5         |  sky130_fd_sc_hd__nand2_1/VPB = 5         
  sky130_fd_sc_hd__nand2_1/VPWR = 5        |  sky130_fd_sc_hd__nand2_1/VPWR = 5        
  sky130_fd_sc_hd__clkinv_4/VPB = 12       |  sky130_fd_sc_hd__clkinv_4/VPB = 12       
  sky130_fd_sc_hd__clkinv_4/VPWR = 12      |  sky130_fd_sc_hd__clkinv_4/VPWR = 12      
  sky130_fd_sc_hd__clkinv_1/VPB = 7        |  sky130_fd_sc_hd__clkinv_1/VPB = 7        
  sky130_fd_sc_hd__clkinv_1/VPWR = 7       |  sky130_fd_sc_hd__clkinv_1/VPWR = 7       
  sky130_fd_sc_hd__clkdlybuf4s50_1/VPB = 1 |  sky130_fd_sc_hd__clkdlybuf4s50_1/VPB = 1 
  sky130_fd_sc_hd__clkdlybuf4s50_1/VPWR =  |  sky130_fd_sc_hd__clkdlybuf4s50_1/VPWR =  
  sky130_fd_sc_hd__nand2_4/VPB = 4         |  sky130_fd_sc_hd__nand2_4/VPB = 4         
  sky130_fd_sc_hd__nand2_4/VPWR = 4        |  sky130_fd_sc_hd__nand2_4/VPWR = 4        
  sky130_fd_sc_hd__dfxbp_1/VPB = 2         |  sky130_fd_sc_hd__dfxbp_1/VPB = 2         
  sky130_fd_sc_hd__dfxbp_1/VPWR = 2        |  sky130_fd_sc_hd__dfxbp_1/VPWR = 2        
  sky130_fd_sc_hd__mux2_1/VPB = 1          |  sky130_fd_sc_hd__mux2_1/VPB = 1          
  sky130_fd_sc_hd__mux2_1/VPWR = 1         |  sky130_fd_sc_hd__mux2_1/VPWR = 1         
  sky130_fd_sc_hd__clkbuf_16/VPB = 16      |  sky130_fd_sc_hd__clkbuf_16/VPB = 16      
  sky130_fd_sc_hd__clkbuf_16/VPWR = 16     |  sky130_fd_sc_hd__clkbuf_16/VPWR = 16     
                                           |  sky130_fd_sc_hd__decap_12/VPWR = 1       
                                           |                                           
Net: VSS                                   |(no matching net)                          
  sky130_fd_sc_hd__decap_4/VGND = 1        |                                           
  sky130_fd_sc_hd__decap_4/VNB = 1         |                                           
  sky130_fd_sc_hd__decap_3/VGND = 1        |                                           
  sky130_fd_sc_hd__decap_3/VNB = 1         |                                           
  sky130_fd_sc_hd__decap_8/VGND = 1        |                                           
  sky130_fd_sc_hd__decap_8/VNB = 1         |                                           
  sky130_fd_sc_hd__decap_12/VGND = 1       |                                           
  sky130_fd_sc_hd__decap_12/VPB = 1        |                                           
  sky130_fd_sc_hd__decap_12/VPWR = 1       |                                           
  sky130_fd_sc_hd__nand2_1/VGND = 5        |                                           
  sky130_fd_sc_hd__nand2_1/VNB = 5         |                                           
  sky130_fd_sc_hd__clkinv_4/VGND = 12      |                                           
  sky130_fd_sc_hd__clkinv_4/VNB = 12       |                                           
  sky130_fd_sc_hd__clkinv_1/VGND = 7       |                                           
  sky130_fd_sc_hd__clkinv_1/VNB = 7        |                                           
  sky130_fd_sc_hd__clkdlybuf4s50_1/VGND =  |                                           
  sky130_fd_sc_hd__clkdlybuf4s50_1/VNB = 1 |                                           
  sky130_fd_sc_hd__nand2_4/VGND = 4        |                                           
  sky130_fd_sc_hd__nand2_4/VNB = 4         |                                           
  sky130_fd_sc_hd__dfxbp_1/VGND = 2        |                                           
  sky130_fd_sc_hd__dfxbp_1/VNB = 2         |                                           
  sky130_fd_sc_hd__mux2_1/VGND = 1         |                                           
  sky130_fd_sc_hd__mux2_1/VNB = 1          |                                           
  sky130_fd_sc_hd__clkbuf_16/VGND = 16     |                                           
  sky130_fd_sc_hd__clkbuf_16/VNB = 16      |                                           
---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------
(no matching net)                          |Net: VSUBS                                 
                                           |  sky130_fd_sc_hd__clkbuf_16/VNB = 16      
                                           |  sky130_fd_sc_hd__decap_4/VNB = 1         
                                           |  sky130_fd_sc_hd__decap_8/VNB = 1         
                                           |  sky130_fd_sc_hd__decap_12/VNB = 1        
                                           |  sky130_fd_sc_hd__clkdlybuf4s50_1/VNB = 1 
                                           |  sky130_fd_sc_hd__clkinv_4/VNB = 12       
                                           |  sky130_fd_sc_hd__nand2_4/VNB = 4         
                                           |  sky130_fd_sc_hd__decap_3/VNB = 1         
                                           |  sky130_fd_sc_hd__dfxbp_1/VNB = 2         
                                           |  sky130_fd_sc_hd__nand2_1/VNB = 5         
                                           |  sky130_fd_sc_hd__clkinv_1/VNB = 7        
                                           |  sky130_fd_sc_hd__mux2_1/VNB = 1          
                                           |                                           
(no matching net)                          |Net: VSS                                   
                                           |  sky130_fd_sc_hd__clkbuf_16/VGND = 16     
                                           |  sky130_fd_sc_hd__decap_4/VGND = 1        
                                           |  sky130_fd_sc_hd__decap_8/VGND = 1        
                                           |  sky130_fd_sc_hd__decap_12/VGND = 1       
                                           |  sky130_fd_sc_hd__clkdlybuf4s50_1/VGND =  
                                           |  sky130_fd_sc_hd__clkinv_4/VGND = 12      
                                           |  sky130_fd_sc_hd__nand2_4/VGND = 4        
                                           |  sky130_fd_sc_hd__decap_3/VGND = 1        
                                           |  sky130_fd_sc_hd__dfxbp_1/VGND = 2        
                                           |  sky130_fd_sc_hd__nand2_1/VGND = 5        
                                           |  sky130_fd_sc_hd__clkinv_1/VGND = 7       
                                           |  sky130_fd_sc_hd__mux2_1/VGND = 1         
---------------------------------------------------------------------------------------
I added decap cells through modifiying the xschem extracted netlist, by adding something like 
x1 VSS VSS VDD VDD sky130_fd_sc_hd__decap_3
. The device number for the clock_v2 subcircuit is correct, however, comparing to your lvs report, mine has an extra net? The designs should be exactly the same. Maybe there's something going on during Magic extraction? I get many warnings after 
extract all
but I didn't find the command to print these warnings in the Magic command reference. Thank you.
image.png
t
Various warnings are typical in any extraction, and the unknown command thing is just something with the keyboard. What is the extra net you're seeing? I am seeing a mismatch in devices now (after pulling your latest) due to the fact that there are no decap_4 or decap_12 devices in analog_top. The only issue I am seeing now probably comes from the shorting of 
out
and 
a_probe_3
and 
a_probe_2
. This is caused by a small label 
out
attached to the two probe signal metal lines, one at roughly (202.7um, 28.53um) and one at (202.7um, -6.44um). Because they have the same name, they are considered shorted unless you use 
extract unique
(which is usually a good idea to use on a final top level layout, to make sure you aren't connecting things virtually by label name instead of physically by metal).
Well, okay, that is not the only issue. After resolving the stray out label, I get this:
Copy code
Instance: clock_v2:6                       |Instance: clock_v2_0
...
  p2 = 8                                   |  p2 = 7
  p2_b = 8                                 |  p2_b = 7
  p2d = 7                                  |  p2d = 8
  clk = 1                                  |  clk = 1
  p2d_b = 7                                |  p2d_b = 8
So it looks like maybe p2 and p2d, and p2_b and p2d_b are swapped between the schematic and layout.
r
I see, checking this right now
I was able to correct the errors and pass LVS. Thank you so much for the help!
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