Hi, does anyone know how to check the capacitors’ capacitance density (capacitance per unit area), leakage current and the nonlinearity? I found there are two kinds of capacitors (mim cap and cap_vpp) in skywater-pdk-libs-sky130_fd_sc_pr. How can I compare the properties of these two caps? Is there any documents? Thanks.

https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#spice-model-information https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#vertical-parallel-plate-vpp-capacitors It is here. 2 fF per um². There are two MiM caps. MiM caps are pretty linear.

Hi Luis, thank you. I saw the capacitance density in the pdk. I am wondering if I miss something. I did not find the information about the nonlinearity and leakage current from the pdk. Just curious how you get the MiM caps are pretty linear?

The non linear capacitors are the MOS ones. They are pretty non linear because the substrate depletion changes with the gate-substrate voltage, so it the dielectric has a variable height. Poly-poly capacitors are non linear because the plates are doped polysilicon, and they have depletion issues too. MiM capacitors are made with metal plates. They are very linear.

Got it. Thank you for the explanation.

For capacitance you have the formula I = C dV/dt. So to simulate non-linearity of a capacitor at imec we used a PWL voltage source. For a linear ramp of the voltage dV/dt is contant meaning the measured current is proportional to the capacitance.

Don't see info here about mimcap leakage so I re-asked https://open-source-silicon.slack.com/archives/C032VUYLL64/p1707506911180299

MiM cap leakage is due to quantum tunneling, and it is negligible for the operation conditions. Research floating gate mosfets, if you want to learn more about this. The main source of leakage of a capacitor usually isn't the cap itself, but the things connected to it.

Ah thanks I had assumed flash memory / fgmos had some special super insulator