I am doing DFT in my SoC, but hold violation occur in my design. Is there any issue with the D Scan Flip Flop in PDK? Without DFT design's timing have no hold violation. @Matt Venn @jeffdi

Are you using Fault to do the DFT? If so, have you tried contacting Manar about it? Scan chains do tend to have issues with hold violations because it's difficult to align the clock to both data inputs simultaneously. There are often places along the scan chain where the scan data or the scan clock have to have delays inserted to avoid race conditions.