************************************ Hello (<!channel>), I wanted to highlight a feature in Caravel that has been added that many of you may not be aware of. The feature allows you to specify the default mode for GPIOs in Caravel upon power-up and reset at design time as part of the tapeout. This means you do not have to configure the IO in order to change the mode (e.g. input vs output, or user vs mgmt access modes). In order to configure the GPIO for your project, copy the file from here to the

verilog/rtl

directory for your project and include this in your repo (or tar archive for chipgnite) when you submit your project. https://github.com/efabless/caravel/blob/44a83f90eb5dbfb8fd620c2f61bf0777a231ddcf/verilog/rtl/user_defines.v Modify the USER_CONFIG_GPIO_X_INIT define statements to the desired mode for each GPIO used. Examples... `define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_OUTPUT `define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_ANALOG ************************************

@jeffdi Does something similar apply to GPIO pins in the analog “caravel_analog_user_project”/Caravan, or only the digital “caravel_user_project”/Caravel? In the past, I physically tied OEB on the GPIO pins as needed from inside the analog user project, and it would nice to avoid that step.

In this case, how are the pins 0 to 4 defined for digital designs?

@Janani Aravind if you look at the file there is a comment:

// The power-on configuration for GPIO 0 to 4 is fixed and cannot be
// modified (allowing the SPI and debug to always be accessible unless
// overridden by a flash program).

@Matt Venn @Dinesh A @jeffdi, I'm using io_out[0] and io_out[4] as outputs for my design. My rtl and GL simulation passes. As my GL passes, can I retain these to be output pins or will it ruin my design after fabrication? Is it safe to use io_out[0] to [4] as output pins?

The gpio configuration applies to caravan as well. Even with setting the oeb, you need to configure ports between mgmt and user areas.

@Jianwei Jia and @Ming Hung Chen

@jeffdi @Tim Edwards It looks like the GPIO defaults on Microwatt MPW6 mostly worked, however I notice an issue with

GPIO_MODE_USER_STD_OUTPUT

h1808

. If I look at I/O 6, bit 0x8 looks wrong:

@Anton Blanchard: @Mitch Bailey found a couple of instances where a few bits were missed because the coordinates supplied in the script were incorrect, so the script failed to find the via that it needed to move. I wonder if this is another such case?

@Anton Blanchard If you're using an older version of caravel,

scripts/gen_gpio_defaults.py

may not be up-to-date. This file was updated on May 9th.

Perhaps the MPW6 tape out isn't using that update? My local tape out was fine (with that patch)

mpw-6b doesn't have the change, but mpw-6c does.

@jeffdi @Tim Edwards could the efabless platform tapeout be using a pre

mpw-6c

version of

caravel

?

@Anton Blanchard - platform tapeout is using

mpw-5e

caravel

.

Thanks @Greg Shuarette. @Mitch Bailey @Tim Edwards it looks like

mpw-5e

has the patch, so something else seems to have caused this.

IIRC, the

gen_gpio_default.py

script only generates cells if they don't exist. If there was a version of the cell created with an older version of the script, it may not have been overwritten with the correct version after the script update.

@Mitch Bailey It looks to have created it, based on the log files. I can't rerun because this is the efabless platform tape out, and we are now blocked from doing new tape outs

@jeffdi: This is a critical error and must be fixed.

Is any one tried by copying this caravel user_defines.v to user project verilog/rtl and over-riding it and tried the rtl simulation in MPW-7?

I don't think it works in sim, only after tapeout

It should work in simulation also, I see issue in caravel file list I have modified the File : mgmt_core_wrapper/verilog/includes/includes.rtl.caravel From: -v $(CARAVEL_PATH)/rtl/user_defines.v To: -v $(USER_PROJECT_VERILOG)/rtl/user_defines.v Now my local simulation passes without any GPIO over-ride though c code

I'll check it too

It worked for me, My Simulation works without Caravel GPIO initialization

It probably only works for you because the defaults work as they are. These defines are applied at tapeout, and Jeff has already said we don't yet have a way to test them.

@Matt Venn I have changed the GPIO default to GPIO_MODE_USER_STD_BIDIRECTIONAL and able to locally simulated it

We have been using it for the last few tapeouts of Microwatt. I worked with @Mitch Bailey to check the final GDS on MPW6 and there was at least one problem (a rounding issue in python that Mitch had previously fixed). No one was able to work out why the error ended up in the design. For simulation I just manually symlink the caravel user_defines.h to my one.