Hi @Harald Pretl , @Stefan Schippers, @Tim Edwards - any best steps video link for fully analog project AND/OR mixed signal project - where we take the LEF , GDS out of the analog and integrate in digital . Thanks

Usually what I do is to first get a full hierarchical netlist from schematic or layout. From the synthesized digital block(s) I get a gate-level SPICE netlist, and then I convert that to an xspice netlist. I have two scripts pulled from my qflow synthesis software: One is

vlog2spice

, which will convert a gate-level verilog netlist to SPICE (If you have layout of the digital block you can also just read that into magic and extract the SPICE netlist). The other is

spi2xspice.py

, which will convert a SPICE netlist with calls to standard cells into its xspice equivalent (using a generic logic look-up table xspice component that I contributed to ngspice some years ago). Finally, I just swap out the digital component subcircuits for the xspice ones. There are some xspice primitives that you can use to apply digital stimulus values from a file. There is also a way to run the testbench from a verilog file using iverilog as a co-simulator, but that feature only exists in an obscure branch of ngspice. Perhaps someone could help bring that feature back into the main ngspice repository, since it's an extremely useful thing to have for a mixed-mode simulation. Xyce also has that capability, and it's in the standard distribution of Xyce, and they have an application note for it in the Xyce documentation at the Sandia National Labs Xyce website. Unfortunately, Xyce has a different way of handling digital logic that is incompatible with xspice (xspice, though, has been in the Berkeley SPICE3 source code for decades).

Maybe I should document this in a more visible place, a yosys script to synthesize verilog to xspice https://github.com/YosysHQ/yosys/pull/2537#issue-785263505

@Tim Edwards those qflow scripts sound really useful. Is this the correct place to get them? https://github.com/RTimothyEdwards/qflow